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From: Kuogee Hsieh <quic_khsieh@quicinc.com>
To: <dri-devel@lists.freedesktop.org>, <robdclark@gmail.com>,
	<sean@poorly.run>, <swboyd@chromium.org>, <vkoul@kernel.org>,
	<daniel@ffwll.ch>, <airlied@linux.ie>, <agross@kernel.org>,
	<dmitry.baryshkov@linaro.org>, <bjorn.andersson@linaro.org>
Cc: Kuogee Hsieh <quic_khsieh@quicinc.com>,
	<quic_abhinavk@quicinc.com>, <quic_aravindh@quicinc.com>,
	<quic_sbillaka@quicinc.com>, <freedreno@lists.freedesktop.org>,
	<linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v12 1/4] drm/msm/dpu: adjust display_v_end for eDP and DP
Date: Fri, 25 Feb 2022 13:23:09 -0800	[thread overview]
Message-ID: <1645824192-29670-2-git-send-email-quic_khsieh@quicinc.com> (raw)
In-Reply-To: <1645824192-29670-1-git-send-email-quic_khsieh@quicinc.com>

The “DP timing” requires the active region to be defined in the
bottom-right corner of the frame dimensions which is different
with DSI. Therefore both display_h_end and display_v_end need
to be adjusted accordingly. However current implementation has
only display_h_end adjusted.

Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>

Fixes: fc3a69ec68d3 ("drm/msm/dpu: intf timing path for displayport")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 116e2b5..284f561 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -148,6 +148,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
 		active_v_end = active_v_start + (p->yres * hsync_period) - 1;
 
 		display_v_start += p->hsync_pulse_width + p->h_back_porch;
+		display_v_end   -= p->h_front_porch; 
 
 		active_hctl = (active_h_end << 16) | active_h_start;
 		display_hctl = active_hctl;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


WARNING: multiple messages have this Message-ID (diff)
From: Kuogee Hsieh <quic_khsieh@quicinc.com>
To: <dri-devel@lists.freedesktop.org>, <robdclark@gmail.com>,
	<sean@poorly.run>, <swboyd@chromium.org>, <vkoul@kernel.org>,
	<daniel@ffwll.ch>, <airlied@linux.ie>, <agross@kernel.org>,
	<dmitry.baryshkov@linaro.org>, <bjorn.andersson@linaro.org>
Cc: quic_sbillaka@quicinc.com, linux-arm-msm@vger.kernel.org,
	quic_abhinavk@quicinc.com, Kuogee Hsieh <quic_khsieh@quicinc.com>,
	quic_aravindh@quicinc.com, freedreno@lists.freedesktop.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v12 1/4] drm/msm/dpu: adjust display_v_end for eDP and DP
Date: Fri, 25 Feb 2022 13:23:09 -0800	[thread overview]
Message-ID: <1645824192-29670-2-git-send-email-quic_khsieh@quicinc.com> (raw)
In-Reply-To: <1645824192-29670-1-git-send-email-quic_khsieh@quicinc.com>

The “DP timing” requires the active region to be defined in the
bottom-right corner of the frame dimensions which is different
with DSI. Therefore both display_h_end and display_v_end need
to be adjusted accordingly. However current implementation has
only display_h_end adjusted.

Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>

Fixes: fc3a69ec68d3 ("drm/msm/dpu: intf timing path for displayport")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 116e2b5..284f561 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -148,6 +148,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
 		active_v_end = active_v_start + (p->yres * hsync_period) - 1;
 
 		display_v_start += p->hsync_pulse_width + p->h_back_porch;
+		display_v_end   -= p->h_front_porch; 
 
 		active_hctl = (active_h_end << 16) | active_h_start;
 		display_hctl = active_hctl;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


  reply	other threads:[~2022-02-25 21:23 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-25 21:23 [PATCH v12 0/4] drm/msm/dpu: enable widebus feature base on chip hardware revision Kuogee Hsieh
2022-02-25 21:23 ` Kuogee Hsieh
2022-02-25 21:23 ` Kuogee Hsieh [this message]
2022-02-25 21:23   ` [PATCH v12 1/4] drm/msm/dpu: adjust display_v_end for eDP and DP Kuogee Hsieh
2022-02-25 21:23 ` [PATCH v12 2/4] drm/msm/dpu: replace BIT(x) with correspond marco define string Kuogee Hsieh
2022-02-25 21:23   ` Kuogee Hsieh
2022-02-25 21:23 ` [PATCH v12 3/4] drm/msm/dpu: revise timing engine programming to support widebus feature Kuogee Hsieh
2022-02-25 21:23   ` Kuogee Hsieh
2022-02-25 21:23 ` [PATCH v12 4/4] drm/msm/dp: enable widebus feature for display port Kuogee Hsieh
2022-02-25 21:23   ` Kuogee Hsieh
2022-02-25 22:17   ` Stephen Boyd
2022-02-25 22:17     ` Stephen Boyd
2022-04-01 20:00     ` Kuogee Hsieh
2022-04-01 20:00       ` Kuogee Hsieh
2022-04-01 20:17       ` Kuogee Hsieh
2022-04-01 20:17         ` Kuogee Hsieh
2022-04-01 21:52   ` Dmitry Baryshkov
2022-04-01 21:52     ` Dmitry Baryshkov

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