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From: Richard Zhu <hongxing.zhu@nxp.com>
To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	l.stach@pengutronix.de, shawnguo@kernel.org,
	lorenzo.pieralisi@arm.com, peng.fan@nxp.com, marex@denx.de,
	marcel.ziswiler@toradex.com, tharvey@gateworks.com,
	frank.li@nxp.com
Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@pengutronix.de,
	linux-imx@nxp.com
Subject: [PATCH v7 3/5] arm64: dts: Add i.MX8MM PCIe EP support
Date: Mon, 30 Jan 2023 11:32:17 +0800	[thread overview]
Message-ID: <1675049539-14976-4-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1675049539-14976-1-git-send-email-hongxing.zhu@nxp.com>

Add i.MX8MM PCIe EP support.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24 +++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 31f4548f85cf..a9552867e547 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1315,6 +1315,30 @@ pcie0: pcie@33800000 {
 			status = "disabled";
 		};
 
+		pcie0_ep: pcie-ep@33800000 {
+			compatible = "fsl,imx8mm-pcie-ep";
+			reg = <0x33800000 0x400000>,
+			      <0x18000000 0x8000000>;
+			reg-names = "dbi", "addr_space";
+			num-lanes = <1>;
+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dma";
+			fsl,max-link-speed = <2>;
+			clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
+				 <&clk IMX8MM_CLK_PCIE1_PHY>,
+				 <&clk IMX8MM_CLK_PCIE1_AUX>;
+			clock-names = "pcie", "pcie_bus", "pcie_aux";
+			power-domains = <&pgc_pcie>;
+			resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+			reset-names = "apps", "turnoff";
+			phys = <&pcie_phy>;
+			phy-names = "pcie-phy";
+			num-ib-windows = <4>;
+			num-ob-windows = <4>;
+			status = "disabled";
+		};
+
 		gpu_3d: gpu@38000000 {
 			compatible = "vivante,gc";
 			reg = <0x38000000 0x8000>;
-- 
2.34.1


WARNING: multiple messages have this Message-ID (diff)
From: Richard Zhu <hongxing.zhu@nxp.com>
To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	l.stach@pengutronix.de, shawnguo@kernel.org,
	lorenzo.pieralisi@arm.com, peng.fan@nxp.com, marex@denx.de,
	marcel.ziswiler@toradex.com, tharvey@gateworks.com,
	frank.li@nxp.com
Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@pengutronix.de,
	linux-imx@nxp.com
Subject: [PATCH v7 3/5] arm64: dts: Add i.MX8MM PCIe EP support
Date: Mon, 30 Jan 2023 11:32:17 +0800	[thread overview]
Message-ID: <1675049539-14976-4-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1675049539-14976-1-git-send-email-hongxing.zhu@nxp.com>

Add i.MX8MM PCIe EP support.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24 +++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 31f4548f85cf..a9552867e547 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1315,6 +1315,30 @@ pcie0: pcie@33800000 {
 			status = "disabled";
 		};
 
+		pcie0_ep: pcie-ep@33800000 {
+			compatible = "fsl,imx8mm-pcie-ep";
+			reg = <0x33800000 0x400000>,
+			      <0x18000000 0x8000000>;
+			reg-names = "dbi", "addr_space";
+			num-lanes = <1>;
+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dma";
+			fsl,max-link-speed = <2>;
+			clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
+				 <&clk IMX8MM_CLK_PCIE1_PHY>,
+				 <&clk IMX8MM_CLK_PCIE1_AUX>;
+			clock-names = "pcie", "pcie_bus", "pcie_aux";
+			power-domains = <&pgc_pcie>;
+			resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+			reset-names = "apps", "turnoff";
+			phys = <&pcie_phy>;
+			phy-names = "pcie-phy";
+			num-ib-windows = <4>;
+			num-ob-windows = <4>;
+			status = "disabled";
+		};
+
 		gpu_3d: gpu@38000000 {
 			compatible = "vivante,gc";
 			reg = <0x38000000 0x8000>;
-- 
2.34.1


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  parent reply	other threads:[~2023-01-30  3:57 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-30  3:32 [PATCH DTS v7 0/5] Add i.MX PCIe EP mode support Richard Zhu
2023-01-30  3:32 ` Richard Zhu
2023-01-30  3:32 ` [PATCH v7 1/5] dt-bindings: imx6q-pcie: Prepare to separate the Endpoint binding document Richard Zhu
2023-01-30  3:32   ` Richard Zhu
2023-01-30 22:31   ` Rob Herring
2023-01-30 22:31     ` Rob Herring
2023-01-31  7:53     ` Hongxing Zhu
2023-01-31  7:53       ` Hongxing Zhu
2023-01-30  3:32 ` [PATCH v7 2/5] dt-bindings: imx6q-pcie: Add schema for i.MX8M PCIe Endpoint modes Richard Zhu
2023-01-30  3:32   ` Richard Zhu
2023-01-30 22:29   ` Rob Herring
2023-01-30 22:29     ` Rob Herring
2023-01-31  7:53     ` Hongxing Zhu
2023-01-31  7:53       ` Hongxing Zhu
2023-01-30  3:32 ` Richard Zhu [this message]
2023-01-30  3:32   ` [PATCH v7 3/5] arm64: dts: Add i.MX8MM PCIe EP support Richard Zhu
2023-01-30  3:32 ` [PATCH v7 4/5] arm64: dts: Add i.MX8MQ " Richard Zhu
2023-01-30  3:32   ` Richard Zhu
2023-01-30  3:32 ` [PATCH v7 5/5] arm64: dts: Add i.MX8MP " Richard Zhu
2023-01-30  3:32   ` Richard Zhu

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