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From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
	dan.j.williams@intel.com, ira.weiny@intel.com,
	vishal.l.verma@intel.com, alison.schofield@intel.com,
	Jonathan.Cameron@huawei.com, dave@stgolabs.net
Subject: [PATCH v15 03/19] acpi: numa: Create enum for memory_target access coordinates indexing
Date: Thu, 21 Dec 2023 15:02:43 -0700	[thread overview]
Message-ID: <170319616332.2212653.3872789279950567889.stgit@djiang5-mobl3> (raw)
In-Reply-To: <170319606771.2212653.5435838660860735129.stgit@djiang5-mobl3>

Create enums to provide named indexing for the access coordinate array.
This is in preparation for adding generic port support which will add a
third index in the array to keep the generic port attributes separate from
the memory attributes.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/numa/hmat.c |   18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c
index 83bc2b69401b..ca7aedfbb5f2 100644
--- a/drivers/acpi/numa/hmat.c
+++ b/drivers/acpi/numa/hmat.c
@@ -58,12 +58,18 @@ struct target_cache {
 	struct node_cache_attrs cache_attrs;
 };
 
+enum {
+	NODE_ACCESS_CLASS_0 = 0,
+	NODE_ACCESS_CLASS_1,
+	NODE_ACCESS_CLASS_MAX,
+};
+
 struct memory_target {
 	struct list_head node;
 	unsigned int memory_pxm;
 	unsigned int processor_pxm;
 	struct resource memregions;
-	struct access_coordinate coord[2];
+	struct access_coordinate coord[NODE_ACCESS_CLASS_MAX];
 	struct list_head caches;
 	struct node_cache_attrs cache_attrs;
 	bool registered;
@@ -339,10 +345,12 @@ static __init int hmat_parse_locality(union acpi_subtable_headers *header,
 			if (mem_hier == ACPI_HMAT_MEMORY) {
 				target = find_mem_target(targs[targ]);
 				if (target && target->processor_pxm == inits[init]) {
-					hmat_update_target_access(target, type, value, 0);
+					hmat_update_target_access(target, type, value,
+								  NODE_ACCESS_CLASS_0);
 					/* If the node has a CPU, update access 1 */
 					if (node_state(pxm_to_node(inits[init]), N_CPU))
-						hmat_update_target_access(target, type, value, 1);
+						hmat_update_target_access(target, type, value,
+									  NODE_ACCESS_CLASS_1);
 				}
 			}
 		}
@@ -726,8 +734,8 @@ static void hmat_register_target(struct memory_target *target)
 	if (!target->registered) {
 		hmat_register_target_initiators(target);
 		hmat_register_target_cache(target);
-		hmat_register_target_perf(target, 0);
-		hmat_register_target_perf(target, 1);
+		hmat_register_target_perf(target, NODE_ACCESS_CLASS_0);
+		hmat_register_target_perf(target, NODE_ACCESS_CLASS_1);
 		target->registered = true;
 	}
 	mutex_unlock(&target_lock);



  parent reply	other threads:[~2023-12-21 22:02 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-21 22:02 [PATCH v15 00/19] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-12-21 22:02 ` [PATCH v15 01/19] lib/firmware_table: tables: Add CDAT table parsing support Dave Jiang
2023-12-21 22:02 ` [PATCH v15 02/19] base/node / acpi: Change 'node_hmem_attrs' to 'access_coordinates' Dave Jiang
2023-12-21 22:02 ` Dave Jiang [this message]
2023-12-21 22:02 ` [PATCH v15 04/19] acpi: numa: Add genport target allocation to the HMAT parsing Dave Jiang
2023-12-21 22:02 ` [PATCH v15 05/19] acpi: Break out nesting for hmat_parse_locality() Dave Jiang
2023-12-21 22:03 ` [PATCH v15 06/19] acpi: numa: Add setting of generic port system locality attributes Dave Jiang
2023-12-21 22:03 ` [PATCH v15 07/19] acpi: numa: Add helper function to retrieve the performance attributes Dave Jiang
2023-12-21 22:03 ` [PATCH v15 08/19] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-12-21 22:03 ` [PATCH v15 09/19] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-12-21 22:03 ` [PATCH v15 10/19] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-12-21 22:03 ` [PATCH v15 11/19] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-12-21 22:03 ` [PATCH v15 12/19] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-12-22 23:31   ` Dan Williams
2023-12-21 22:03 ` [PATCH v15 13/19] tools/testing/cxl: Add hostbridge UID string for cxl_test mock hb devices Dave Jiang
2023-12-21 22:03 ` [PATCH v15 14/19] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-12-21 22:03 ` [PATCH v15 15/19] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-12-21 22:04 ` [PATCH v15 16/19] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-12-21 22:04 ` [PATCH v15 17/19] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-12-21 22:04 ` [PATCH v15 18/19] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-12-21 22:04 ` [PATCH v15 19/19] cxl: Check qos_class validity on memdev probe Dave Jiang
2024-01-04 13:19   ` Robert Richter
2024-01-04 16:12     ` Dave Jiang
2023-12-29  0:04 ` [PATCH v15 00/19] cxl: Add support for QTG ID retrieval for CXL subsystem Bjorn Helgaas
2024-01-04  1:00   ` Dan Williams

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