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From: Yanteng Si <siyanteng@loongson.cn>
To: tiwai@suse.com
Cc: Yanteng Si <siyanteng@loongson.cn>,
	perex@perex.cz, chenhuacai@loongson.cn,
	alsa-devel@alsa-project.org, loongarch@lists.linux.dev,
	loongson-kernel@lists.loongnix.cn,
	Yingkun Meng <mengyingkun@loongson.cn>
Subject: [PATCH RESEND v3 4/4] ALSA: hda/intel: Workaround for WALLCLK register for loongson controller
Date: Wed,  7 Jun 2023 17:21:52 +0800	[thread overview]
Message-ID: <185df71ef413ab190460eb377703214ee7288aeb.1686128807.git.siyanteng@loongson.cn> (raw)
In-Reply-To: <cover.1686128807.git.siyanteng@loongson.cn>

On loongson controller, the value of WALLCLK register
is always 0, which is meaningless, so we return directly.

Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Yingkun Meng <mengyingkun@loongson.cn>
---
 sound/pci/hda/hda_intel.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index fc4787c7782a..ef831770ca7d 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -655,6 +655,13 @@ static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 	unsigned int pos;
 	snd_pcm_uframes_t hwptr, target;
 
+	/*
+	 * The value of the WALLCLK register is always 0
+	 * on the Loongson controller, so we return directly.
+	 */
+	if (chip->driver_type == AZX_DRIVER_LOONGSON)
+		return 1;
+
 	wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 	if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 		return -1;	/* bogus (too early) interrupt */
-- 
2.31.4


  parent reply	other threads:[~2023-06-07  9:22 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-07  9:21 [PATCH RESEND v3 0/4] Add Loongson HD Audio support Yanteng Si
2023-06-07  9:21 ` [PATCH RESEND v3 1/4] ALSA: hda: Add Loongson LS7A HD-Audio support Yanteng Si
2023-06-07  9:21 ` [PATCH RESEND v3 2/4] ALSA: hda: Using polling mode for loongson controller by default Yanteng Si
2023-06-07  9:21 ` [PATCH RESEND v3 3/4] ALSA: hda: Workaround for SDnCTL register on loongson Yanteng Si
2023-06-07  9:21 ` Yanteng Si [this message]
2023-06-07  9:27 ` [PATCH RESEND v3 0/4] Add Loongson HD Audio support Huacai Chen
2023-06-07 10:44 ` Takashi Iwai

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