From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH] drm/i915: remove unnecessary PIPE_CONTROL cache flushing
Date: Wed, 21 Apr 2010 13:02:58 -0700 [thread overview]
Message-ID: <20100421130258.510a6fd9@virtuousgeek.org> (raw)
In-Reply-To: <1271875166-13084-6-git-send-email-jbarnes@virtuousgeek.org>
Was better safe than sorry, but it appears these bits aren't necessary.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_gem.c | 5 +----
1 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 56ff905..5a34b71 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1637,8 +1637,7 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
* an interrupt.
*/
BEGIN_LP_RING(32);
- OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
- PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
+ OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE);
OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
OUT_RING(seqno);
OUT_RING(0);
@@ -1654,7 +1653,6 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
scratch_addr += 128;
PIPE_CONTROL_FLUSH(scratch_addr);
OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
- PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
PIPE_CONTROL_NOTIFY);
OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
OUT_RING(seqno);
@@ -1664,7 +1662,6 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
/* Don't penalize non-ilk parts with the extra writes */
BEGIN_LP_RING(4);
OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
- PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
PIPE_CONTROL_NOTIFY);
OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
OUT_RING(seqno);
--
1.7.0.1
prev parent reply other threads:[~2010-04-21 20:01 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-04-21 18:39 Use PIPE_CONTROL where possible Jesse Barnes
2010-04-21 18:39 ` [PATCH 1/5] drm/i915: cleanup FBC buffers at unload time Jesse Barnes
2010-04-21 18:39 ` [PATCH 2/5] drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge Jesse Barnes
2010-04-21 18:39 ` [PATCH 3/5] drm/i915: use PIPE_CONTROL to retire commands Jesse Barnes
2010-04-29 21:26 ` Eric Anholt
2010-05-03 19:41 ` Jesse Barnes
2010-04-21 18:39 ` [PATCH 4/5] drm/i915: use PIPE_CONTROL for GEM domain flushing Jesse Barnes
2010-04-21 18:39 ` [PATCH 5/5] drm/i915: enable PIPE_CONTROL on all 965 class chips Jesse Barnes
2010-04-21 19:49 ` [PATCH] drm/i915: avoid unnecessary PIPE_CONTROL flushing on non-Ironlake Jesse Barnes
2010-04-21 20:02 ` Jesse Barnes [this message]
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