From: "Heiko Stübner" <heiko@sntech.de> To: Kukjin Kim <kgene.kim@samsung.com> Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 5/6] ARM: S3C24XX: transform s3c2442 irqs into new structure Date: Wed, 6 Feb 2013 00:14:49 +0100 [thread overview] Message-ID: <201302060014.49937.heiko@sntech.de> (raw) In-Reply-To: <201302060010.53929.heiko@sntech.de> Simply declare a correct mapping structure to use the common irq code. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- arch/arm/mach-s3c24xx/irq.c | 78 ++++++++++++++++++++++++++++++++++-------- 1 files changed, 63 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c index 998e6a8..01358a5 100644 --- a/arch/arm/mach-s3c24xx/irq.c +++ b/arch/arm/mach-s3c24xx/irq.c @@ -879,27 +879,75 @@ void __init s3c2440_init_irq(void) #endif #ifdef CONFIG_CPU_S3C2442 -void __init s3c2442_init_irq(void) -{ - unsigned int irqno; +static struct s3c_irq_data init_s3c2442base[32] = { + { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ + { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ + { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ + { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ +}; - s3c24xx_init_irq(); +static struct s3c_irq_data init_s3c2442subint[32] = { + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* TC */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* ADC */ +}; - irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip, - handle_level_irq); - set_irq_flags(IRQ_NFCON, IRQF_VALID); +void __init s3c2442_init_irq(void) +{ + struct s3c_irq_intc *main_intc; - /* add chained handler for camera */ + pr_info("S3C2442: IRQ Support\n"); - irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip, - handle_level_irq); - irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam); +#ifdef CONFIG_FIQ + init_FIQ(FIQ_START); +#endif - for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { - irq_set_chip_and_handler(irqno, &s3c_irq_cam, - handle_level_irq); - set_irq_flags(irqno, IRQF_VALID); + main_intc = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL, 0x4a000000); + if (IS_ERR(main_intc)) { + pr_err("irq: could not create main interrupt controller\n"); + return; } + + s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); + s3c24xx_init_intc(NULL, &init_s3c2442subint[0], main_intc, 0x4a000018); } #endif -- 1.7.2.3
WARNING: multiple messages have this Message-ID (diff)
From: heiko@sntech.de (Heiko Stübner) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/6] ARM: S3C24XX: transform s3c2442 irqs into new structure Date: Wed, 6 Feb 2013 00:14:49 +0100 [thread overview] Message-ID: <201302060014.49937.heiko@sntech.de> (raw) In-Reply-To: <201302060010.53929.heiko@sntech.de> Simply declare a correct mapping structure to use the common irq code. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- arch/arm/mach-s3c24xx/irq.c | 78 ++++++++++++++++++++++++++++++++++-------- 1 files changed, 63 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c index 998e6a8..01358a5 100644 --- a/arch/arm/mach-s3c24xx/irq.c +++ b/arch/arm/mach-s3c24xx/irq.c @@ -879,27 +879,75 @@ void __init s3c2440_init_irq(void) #endif #ifdef CONFIG_CPU_S3C2442 -void __init s3c2442_init_irq(void) -{ - unsigned int irqno; +static struct s3c_irq_data init_s3c2442base[32] = { + { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ + { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ + { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ + { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ +}; - s3c24xx_init_irq(); +static struct s3c_irq_data init_s3c2442subint[32] = { + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* TC */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* ADC */ +}; - irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip, - handle_level_irq); - set_irq_flags(IRQ_NFCON, IRQF_VALID); +void __init s3c2442_init_irq(void) +{ + struct s3c_irq_intc *main_intc; - /* add chained handler for camera */ + pr_info("S3C2442: IRQ Support\n"); - irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip, - handle_level_irq); - irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam); +#ifdef CONFIG_FIQ + init_FIQ(FIQ_START); +#endif - for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { - irq_set_chip_and_handler(irqno, &s3c_irq_cam, - handle_level_irq); - set_irq_flags(irqno, IRQF_VALID); + main_intc = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL, 0x4a000000); + if (IS_ERR(main_intc)) { + pr_err("irq: could not create main interrupt controller\n"); + return; } + + s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); + s3c24xx_init_intc(NULL, &init_s3c2442subint[0], main_intc, 0x4a000018); } #endif -- 1.7.2.3
next prev parent reply other threads:[~2013-02-05 23:14 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-02-05 23:10 [PATCH 0/6] ARM: S3C24XX: Move s3c2440 and s3c2442 into new irq structure Heiko Stübner 2013-02-05 23:10 ` Heiko Stübner 2013-02-05 23:11 ` [PATCH 1/6] ARM: S3C24XX: move s3c244x irq init to common irq code Heiko Stübner 2013-02-05 23:11 ` Heiko Stübner 2013-02-05 23:12 ` [PATCH 2/6] ARM: S3C24XX: create dedicated irq init functions for s3c2440 and s3c2442 Heiko Stübner 2013-02-05 23:12 ` Heiko Stübner 2013-02-05 23:13 ` [PATCH 3/6] ARM: S3C24XX: move s3c2440 irqs to common irq code Heiko Stübner 2013-02-05 23:13 ` Heiko Stübner 2013-02-05 23:14 ` [PATCH 4/6] ARM: S3C24XX: integrate s3c2440 irqs into common init Heiko Stübner 2013-02-05 23:14 ` Heiko Stübner 2013-02-05 23:14 ` Heiko Stübner [this message] 2013-02-05 23:14 ` [PATCH 5/6] ARM: S3C24XX: transform s3c2442 irqs into new structure Heiko Stübner 2013-02-05 23:16 ` [PATCH 6/6] ARM: S3C24XX: transform s3c2440 " Heiko Stübner 2013-02-05 23:16 ` Heiko Stübner
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