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From: Christoffer Dall <christoffer.dall@linaro.org>
To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org
Cc: Marc Zyngier <marc.zyngier@arm.com>,
	kvm@vger.kernel.org, Vladimir Murzin <vladimir.murzin@arm.com>,
	Christoffer Dall <christoffer.dall@linaro.org>
Subject: [PULL 11/12] arm64: KVM: remove misleading comment on pmu status
Date: Wed, 17 Aug 2016 21:38:58 +0200	[thread overview]
Message-ID: <20160817193859.15726-12-christoffer.dall@linaro.org> (raw)
In-Reply-To: <20160817193859.15726-1-christoffer.dall@linaro.org>

From: Vladimir Murzin <vladimir.murzin@arm.com>

Comment about how PMU access is handled is not relavant since v4.6
where proper PMU support was added in.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
 arch/arm64/kvm/sys_regs.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index b0b225c..af5ea86 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -823,14 +823,6 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
  * Architected system registers.
  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
  *
- * We could trap ID_DFR0 and tell the guest we don't support performance
- * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
- * NAKed, so it will read the PMCR anyway.
- *
- * Therefore we tell the guest we have 0 counters.  Unfortunately, we
- * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
- * all PM registers, which doesn't crash the guest kernel at least.
- *
  * Debug handling: We do trap most, if not all debug related system
  * registers. The implementation is good enough to ensure that a guest
  * can use these with minimal performance degradation. The drawback is
-- 
2.9.0


WARNING: multiple messages have this Message-ID (diff)
From: christoffer.dall@linaro.org (Christoffer Dall)
To: linux-arm-kernel@lists.infradead.org
Subject: [PULL 11/12] arm64: KVM: remove misleading comment on pmu status
Date: Wed, 17 Aug 2016 21:38:58 +0200	[thread overview]
Message-ID: <20160817193859.15726-12-christoffer.dall@linaro.org> (raw)
In-Reply-To: <20160817193859.15726-1-christoffer.dall@linaro.org>

From: Vladimir Murzin <vladimir.murzin@arm.com>

Comment about how PMU access is handled is not relavant since v4.6
where proper PMU support was added in.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
 arch/arm64/kvm/sys_regs.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index b0b225c..af5ea86 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -823,14 +823,6 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
  * Architected system registers.
  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
  *
- * We could trap ID_DFR0 and tell the guest we don't support performance
- * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
- * NAKed, so it will read the PMCR anyway.
- *
- * Therefore we tell the guest we have 0 counters.  Unfortunately, we
- * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
- * all PM registers, which doesn't crash the guest kernel at least.
- *
  * Debug handling: We do trap most, if not all debug related system
  * registers. The implementation is good enough to ensure that a guest
  * can use these with minimal performance degradation. The drawback is
-- 
2.9.0

  parent reply	other threads:[~2016-08-17 19:37 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-17 19:38 [PULL 00/12] KVM/ARM Fixes for v4.8-rc3 Christoffer Dall
2016-08-17 19:38 ` Christoffer Dall
2016-08-17 19:38 ` [PULL 01/12] KVM: arm64: ITS: return 1 on successful MSI injection Christoffer Dall
2016-08-17 19:38   ` Christoffer Dall
2016-08-17 19:38 ` [PULL 02/12] KVM: arm64: vgic-its: Handle errors from vgic_add_lpi Christoffer Dall
2016-08-17 19:38   ` Christoffer Dall
2016-08-17 19:38 ` [PULL 03/12] KVM: arm64: vgic-its: Plug race in vgic_put_irq Christoffer Dall
2016-08-17 19:38   ` Christoffer Dall
2016-08-17 19:38 ` [PULL 04/12] KVM: arm64: vgic-its: Make updates to propbaser/pendbaser atomic Christoffer Dall
2016-08-17 19:38   ` Christoffer Dall
2016-08-17 19:38 ` [PULL 05/12] KVM: arm64: ITS: move ITS registration into first VCPU run Christoffer Dall
2016-08-17 19:38   ` Christoffer Dall
2016-08-17 19:38 ` [PULL 06/12] KVM: arm64: check for ITS device on MSI injection Christoffer Dall
2016-08-17 19:38   ` Christoffer Dall
2016-08-17 19:38 ` [PULL 07/12] KVM: arm64: ITS: avoid re-mapping LPIs Christoffer Dall
2016-08-17 19:38   ` Christoffer Dall
2016-08-17 19:38 ` [PULL 08/12] KVM: arm/arm64: Change misleading use of is_error_pfn Christoffer Dall
2016-08-17 19:38   ` Christoffer Dall
2016-08-17 19:38 ` [PULL 09/12] arm64: Document workaround for Cortex-A72 erratum #853709 Christoffer Dall
2016-08-17 19:38   ` Christoffer Dall
2016-08-17 19:38 ` [PULL 10/12] KVM: arm/arm64: timer: Workaround misconfigured timer interrupt Christoffer Dall
2016-08-17 19:38   ` Christoffer Dall
2016-08-17 19:38 ` Christoffer Dall [this message]
2016-08-17 19:38   ` [PULL 11/12] arm64: KVM: remove misleading comment on pmu status Christoffer Dall
2016-08-17 19:38 ` [PULL 12/12] arm64: KVM: report configured SRE value to 32-bit world Christoffer Dall
2016-08-17 19:38   ` Christoffer Dall
2016-08-18 10:19 ` [PULL 00/12] KVM/ARM Fixes for v4.8-rc3 Paolo Bonzini
2016-08-18 10:19   ` Paolo Bonzini

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