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From: Stefan Agner <stefan@agner.ch>
To: meng.yi@nxp.com, dri-devel@lists.freedesktop.org
Cc: alison.wang@freescale.com, jianwei.wang.chn@gmail.com,
	linux-kernel@vger.kernel.org, Stefan Agner <stefan@agner.ch>
Subject: [PATCH v3 3/5] drm/fsl-dcu: do not transfer registers in mode_set_nofb
Date: Mon, 17 Oct 2016 14:33:19 -0700	[thread overview]
Message-ID: <20161017213321.8074-4-stefan@agner.ch> (raw)
In-Reply-To: <20161017213321.8074-1-stefan@agner.ch>

Do not schedule a transfer of mode settings early. Modes should
get applied on on CRTC enable where we also enable the pixel clock.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 3371635..5ad1d68 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -116,8 +116,6 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 		     DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
 		     DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
 		     DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
-	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
-		     DCU_UPDATE_MODE_READREG);
 	return;
 }
 
-- 
2.10.0

WARNING: multiple messages have this Message-ID (diff)
From: Stefan Agner <stefan@agner.ch>
To: meng.yi@nxp.com, dri-devel@lists.freedesktop.org
Cc: jianwei.wang.chn@gmail.com, linux-kernel@vger.kernel.org,
	alison.wang@freescale.com
Subject: [PATCH v3 3/5] drm/fsl-dcu: do not transfer registers in mode_set_nofb
Date: Mon, 17 Oct 2016 14:33:19 -0700	[thread overview]
Message-ID: <20161017213321.8074-4-stefan@agner.ch> (raw)
In-Reply-To: <20161017213321.8074-1-stefan@agner.ch>

Do not schedule a transfer of mode settings early. Modes should
get applied on on CRTC enable where we also enable the pixel clock.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 3371635..5ad1d68 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -116,8 +116,6 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 		     DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
 		     DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
 		     DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
-	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
-		     DCU_UPDATE_MODE_READREG);
 	return;
 }
 
-- 
2.10.0

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  parent reply	other threads:[~2016-10-17 21:34 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-17 21:33 [PATCH v3 0/5] drm/fsl-dcu: initialization fixes Stefan Agner
2016-10-17 21:33 ` Stefan Agner
2016-10-17 21:33 ` [PATCH v3 1/5] drm/fsl-dcu: enable TCON bypass mode by default Stefan Agner
2016-10-17 21:33   ` Stefan Agner
2016-10-19  9:35   ` Meng Yi
2016-10-20  0:01     ` Stefan Agner
2016-10-20  0:01       ` Stefan Agner
2016-10-17 21:33 ` [PATCH v3 2/5] drm/fsl-dcu: do not transfer registers on plane init Stefan Agner
2016-10-17 21:33   ` Stefan Agner
2016-10-17 21:33 ` Stefan Agner [this message]
2016-10-17 21:33   ` [PATCH v3 3/5] drm/fsl-dcu: do not transfer registers in mode_set_nofb Stefan Agner
2016-10-17 21:33 ` [PATCH v3 4/5] drm/fsl-dcu: enable pixel clock when enabling CRTC Stefan Agner
2016-10-17 21:33   ` Stefan Agner
2016-10-17 21:33 ` [PATCH v3 5/5] drm/fsl-dcu: only init fbdev if required Stefan Agner
2016-10-17 21:33   ` Stefan Agner
2016-10-18  7:44   ` Daniel Vetter
2016-10-18  7:44     ` Daniel Vetter
2016-10-18 17:42     ` Stefan Agner
2016-10-18 17:42       ` Stefan Agner
2016-10-19  7:42       ` Daniel Vetter
2016-10-19  7:42         ` Daniel Vetter

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