From: Robert Bragg <robert@sixbynine.org>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org,
Matthew Auld <matthew.william.auld@gmail.com>,
Sourab Gupta <sourab.gupta@intel.com>,
Daniel Vetter <daniel.vetter@intel.com>,
Robert Bragg <robert@sixbynine.org>
Subject: [PATCH v6 02/11] drm/i915: rename OACONTROL GEN7_OACONTROL
Date: Thu, 20 Oct 2016 22:19:01 +0100 [thread overview]
Message-ID: <20161020211910.4723-2-robert@sixbynine.org> (raw)
In-Reply-To: <20161020211910.4723-1-robert@sixbynine.org>
OACONTROL changes quite a bit for gen8, with some bits split out into a
per-context OACTXCONTROL register. Rename now before adding more gen7 OA
registers
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 3e74fb3..68e07a1 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2159,7 +2159,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_F(0x2290, 8, 0, 0, 0, D_HSW_PLUS, NULL, NULL);
- MMIO_D(OACONTROL, D_HSW);
+ MMIO_D(GEN7_OACONTROL, D_HSW);
MMIO_D(0x2b00, D_BDW_PLUS);
MMIO_D(0x2360, D_BDW_PLUS);
MMIO_F(0x5200, 32, 0, 0, 0, D_ALL, NULL, NULL);
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index f191d7b..fe34470 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -450,7 +450,7 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
REG64(PS_INVOCATION_COUNT),
REG64(PS_DEPTH_COUNT),
REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
- REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */
+ REG32(GEN7_OACONTROL), /* Only allowed for LRI and SRM. See below. */
REG64(MI_PREDICATE_SRC0),
REG64(MI_PREDICATE_SRC1),
REG32(GEN7_3DPRIM_END_OFFSET),
@@ -1108,7 +1108,7 @@ static bool check_cmd(const struct intel_engine_cs *engine,
* to the register. Hence, limit OACONTROL writes to
* only MI_LOAD_REGISTER_IMM commands.
*/
- if (reg_addr == i915_mmio_reg_offset(OACONTROL)) {
+ if (reg_addr == i915_mmio_reg_offset(GEN7_OACONTROL)) {
if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
return false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 00efaa1..0ad7f03 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -615,7 +615,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
-#define OACONTROL _MMIO(0x2360)
+#define GEN7_OACONTROL _MMIO(0x2360)
#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
--
2.10.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2016-10-20 21:19 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-20 21:19 [PATCH v6 01/11] drm/i915: Add i915 perf infrastructure Robert Bragg
2016-10-20 21:19 ` Robert Bragg [this message]
2016-10-20 21:19 ` [PATCH v6 03/11] drm/i915: return EACCES for check_cmd() failures Robert Bragg
2016-10-21 9:56 ` Chris Wilson
2016-10-21 19:38 ` [PATCH] igt/gem_exec_parse: update for version 8 changes Robert Bragg
2016-10-20 21:19 ` [PATCH v6 04/11] drm/i915: don't whitelist oacontrol in cmd parser Robert Bragg
2016-10-20 21:19 ` [PATCH v6 05/11] drm/i915: Add 'render basic' Haswell OA unit config Robert Bragg
2016-10-20 21:19 ` [PATCH v6 06/11] drm/i915: Enable i915 perf stream for Haswell OA unit Robert Bragg
2016-10-20 22:10 ` Chris Wilson
2016-10-21 16:01 ` Robert Bragg
2016-10-21 18:19 ` Robert Bragg
2016-10-21 18:24 ` [PATCH] " Robert Bragg
2016-10-20 21:19 ` [PATCH v6 07/11] drm/i915: advertise available metrics via sysfs Robert Bragg
2016-10-20 21:19 ` [PATCH v6 08/11] drm/i915: Add dev.i915.perf_stream_paranoid sysctl option Robert Bragg
2016-10-20 21:19 ` [PATCH v6 09/11] drm/i915: add oa_event_min_timer_exponent sysctl Robert Bragg
2016-10-20 21:19 ` [PATCH v6 10/11] drm/i915: Add more Haswell OA metric sets Robert Bragg
2016-10-20 21:19 ` [PATCH v6 11/11] drm/i915: Add a kerneldoc summary for i915_perf.c Robert Bragg
2016-10-20 21:47 ` ✗ Fi.CI.BAT: failure for series starting with [v6,01/11] drm/i915: Add i915 perf infrastructure Patchwork
2016-10-21 18:46 ` ✗ Fi.CI.BAT: failure for series starting with [v6,01/11] drm/i915: Add i915 perf infrastructure (rev2) Patchwork
2016-10-21 19:22 ` Saarinen, Jani
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20161020211910.4723-2-robert@sixbynine.org \
--to=robert@sixbynine.org \
--cc=daniel.vetter@intel.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
--cc=matthew.william.auld@gmail.com \
--cc=sourab.gupta@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.