From: Stafford Horne <shorne@gmail.com> To: Jia Liu <proljc@gmail.com>, qemu-devel@nongnu.org Cc: Stafford Horne <shorne@gmail.com>, qemu-trivial@nongnu.org, openrisc@lists.librecores.org Subject: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers Date: Sat, 14 Jan 2017 07:00:28 +0900 [thread overview] Message-ID: <20170113220028.29687-1-shorne@gmail.com> (raw) I am working on testing instruction emulation patches for the linux kernel. During testing I found these 2 issues: - sets DSX (delay slot exception) but never clears it - EEAR for illegal insns should point to the bad exception (as per openrisc spec) but its not This patch fixes these two issues by clearing the DSX flag when not in a delay slot and by setting EEAR to exception PC when handling illegal instruction exceptions. After this patch the openrisc kernel with latest patches boots great on qemu and instruction emulation works. Cc: qemu-trivial@nongnu.org Cc: openrisc@lists.librecores.org Signed-off-by: Stafford Horne <shorne@gmail.com> --- target/openrisc/interrupt.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 5fe3f11..e1b0142 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -38,10 +38,17 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->flags &= ~D_FLAG; env->sr |= SR_DSX; env->epcr -= 4; + } else { + env->sr &= ~SR_DSX; } if (cs->exception_index == EXCP_SYSCALL) { env->epcr += 4; } + /* When we have an illegal instruction the error effective address + shall be set to the illegal instruction address. */ + if (cs->exception_index == EXCP_ILLEGAL) { + env->eear = env->pc; + } /* For machine-state changed between user-mode and supervisor mode, we need flush TLB when we enter&exit EXCP. */ -- 2.9.3
WARNING: multiple messages have this Message-ID (diff)
From: Stafford Horne <shorne@gmail.com> To: openrisc@lists.librecores.org Subject: [OpenRISC] [PATCH] target-openrisc: Fix exception handling status registers Date: Sat, 14 Jan 2017 07:00:28 +0900 [thread overview] Message-ID: <20170113220028.29687-1-shorne@gmail.com> (raw) I am working on testing instruction emulation patches for the linux kernel. During testing I found these 2 issues: - sets DSX (delay slot exception) but never clears it - EEAR for illegal insns should point to the bad exception (as per openrisc spec) but its not This patch fixes these two issues by clearing the DSX flag when not in a delay slot and by setting EEAR to exception PC when handling illegal instruction exceptions. After this patch the openrisc kernel with latest patches boots great on qemu and instruction emulation works. Cc: qemu-trivial at nongnu.org Cc: openrisc at lists.librecores.org Signed-off-by: Stafford Horne <shorne@gmail.com> --- target/openrisc/interrupt.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 5fe3f11..e1b0142 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -38,10 +38,17 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->flags &= ~D_FLAG; env->sr |= SR_DSX; env->epcr -= 4; + } else { + env->sr &= ~SR_DSX; } if (cs->exception_index == EXCP_SYSCALL) { env->epcr += 4; } + /* When we have an illegal instruction the error effective address + shall be set to the illegal instruction address. */ + if (cs->exception_index == EXCP_ILLEGAL) { + env->eear = env->pc; + } /* For machine-state changed between user-mode and supervisor mode, we need flush TLB when we enter&exit EXCP. */ -- 2.9.3
next reply other threads:[~2017-01-13 22:00 UTC|newest] Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-01-13 22:00 Stafford Horne [this message] 2017-01-13 22:00 ` [OpenRISC] [PATCH] target-openrisc: Fix exception handling status registers Stafford Horne -- strict thread matches above, loose matches on Subject: below -- 2017-01-13 21:57 Stafford Horne 2017-01-13 22:02 ` Stafford Horne 2017-01-14 4:29 ` Jia Liu 2017-01-14 8:04 ` [Qemu-devel] " Stafford Horne 2017-01-20 16:39 ` Stafford Horne 2017-01-23 18:08 ` Richard Henderson 2017-01-24 10:26 ` Stafford Horne 2017-01-24 18:32 ` Richard Henderson 2017-01-25 12:34 ` Stafford Horne 2017-01-25 17:27 ` Richard Henderson 2017-01-26 13:12 ` Stafford Horne 2017-01-26 17:26 ` Richard Henderson 2017-01-26 22:01 ` Stafford Horne 2017-02-01 10:04 ` Stafford Horne 2017-02-01 18:15 ` Richard Henderson 2017-02-02 14:34 ` Stafford Horne 2017-02-03 15:14 ` Stafford Horne 2017-02-07 2:36 ` Richard Henderson 2017-02-07 5:53 ` Richard Henderson 2017-02-08 14:01 ` Stafford Horne 2017-02-08 16:38 ` Stafford Horne 2017-02-08 20:38 ` Richard Henderson
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