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From: Vinicius Maciel <viniciusfre-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Cc: broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org,
	wens-jdAy2FN1RRM@public.gmane.org,
	linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	siarhei.siamashka-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
	Vinicius Maciel
	<viniciusfre-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: [PATCH v2] ARM: spi/sun7i: Add Master Sample Data Mode for SPI
Date: Sat, 11 Feb 2017 00:54:47 -0300	[thread overview]
Message-ID: <20170211035447.3819-1-viniciusfre@gmail.com> (raw)

In order to work appropriately, the max11043 ADC chip and probably
others, needs SPI master samples the data at the correct edge. From
max11043 datasheet: "The data at DIN is latched on the rising edge
of SCLK". Same to DOUT.

This patch add Master Sample Data Mode bit in normal sample mode.
It will affect only A20.

Signed-off-by: Vinicius Maciel <viniciusfre-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Siarhei Siamashka <siarhei.siamashka-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/spi/spi-sun4i.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
index c5cd635c28f3..6325be2ce8d9 100644
--- a/drivers/spi/spi-sun4i.c
+++ b/drivers/spi/spi-sun4i.c
@@ -44,6 +44,7 @@
 #define SUN4I_CTL_CS_MANUAL			BIT(16)
 #define SUN4I_CTL_CS_LEVEL			BIT(17)
 #define SUN4I_CTL_TP				BIT(18)
+#define SUN4I_CTL_SDM				BIT(20)
 
 #define SUN4I_INT_CTL_REG		0x0c
 #define SUN4I_INT_CTL_RF_F34			BIT(4)
@@ -407,7 +408,8 @@ static int sun4i_spi_runtime_resume(struct device *dev)
 	}
 
 	sun4i_spi_write(sspi, SUN4I_CTL_REG,
-			SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
+			SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP |
+			SUN4I_CTL_SDM);
 
 	return 0;
 
-- 
2.11.0

WARNING: multiple messages have this Message-ID (diff)
From: viniciusfre@gmail.com (Vinicius Maciel)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] ARM: spi/sun7i: Add Master Sample Data Mode for SPI
Date: Sat, 11 Feb 2017 00:54:47 -0300	[thread overview]
Message-ID: <20170211035447.3819-1-viniciusfre@gmail.com> (raw)

In order to work appropriately, the max11043 ADC chip and probably
others, needs SPI master samples the data at the correct edge. From
max11043 datasheet: "The data at DIN is latched on the rising edge
of SCLK". Same to DOUT.

This patch add Master Sample Data Mode bit in normal sample mode.
It will affect only A20.

Signed-off-by: Vinicius Maciel <viniciusfre@gmail.com>
Reviewed-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
---
 drivers/spi/spi-sun4i.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
index c5cd635c28f3..6325be2ce8d9 100644
--- a/drivers/spi/spi-sun4i.c
+++ b/drivers/spi/spi-sun4i.c
@@ -44,6 +44,7 @@
 #define SUN4I_CTL_CS_MANUAL			BIT(16)
 #define SUN4I_CTL_CS_LEVEL			BIT(17)
 #define SUN4I_CTL_TP				BIT(18)
+#define SUN4I_CTL_SDM				BIT(20)
 
 #define SUN4I_INT_CTL_REG		0x0c
 #define SUN4I_INT_CTL_RF_F34			BIT(4)
@@ -407,7 +408,8 @@ static int sun4i_spi_runtime_resume(struct device *dev)
 	}
 
 	sun4i_spi_write(sspi, SUN4I_CTL_REG,
-			SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
+			SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP |
+			SUN4I_CTL_SDM);
 
 	return 0;
 
-- 
2.11.0

             reply	other threads:[~2017-02-11  3:54 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-11  3:54 Vinicius Maciel [this message]
2017-02-11  3:54 ` [PATCH v2] ARM: spi/sun7i: Add Master Sample Data Mode for SPI Vinicius Maciel
     [not found] ` <20170211035447.3819-1-viniciusfre-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-02-13  7:12   ` Maxime Ripard
2017-02-13  7:12     ` Maxime Ripard
2017-02-13 12:52   ` Mark Brown
2017-02-13 12:52     ` Mark Brown
     [not found]     ` <20170213125239.f5vsxrfwz5t6gqyp-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2017-02-26 14:10       ` Vinicius Maciel
     [not found]         ` <186c0f31-01d0-4a1b-889b-a390a57bd1d9-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org>
2017-03-02 20:44           ` Siarhei Siamashka
2017-03-02 20:44             ` Siarhei Siamashka
2017-03-02 22:00             ` Vinicius Maciel
2017-02-11  6:58 Icenowy Zheng

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