From: Heiko Stuebner <heiko@sntech.de>
To: linux-rockchip@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
sboyd@codeaurora.org, mturquette@baylibre.com,
Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH 3/4] clk: rockchip: assign the SCLK_UARTPLL clock id on rk3036
Date: Tue, 28 Feb 2017 06:14:19 +0100 [thread overview]
Message-ID: <20170228051420.7214-4-heiko@sntech.de> (raw)
In-Reply-To: <20170228051420.7214-1-heiko@sntech.de>
Assign it to the matching clock in the clock driver.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/clk/rockchip/clk-rk3036.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index dcde70f4c105..d10934b63a0d 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -242,7 +242,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(2), 7, 1, MFLAGS,
RK2928_CLKGATE_CON(2), 5, GFLAGS),
- MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
+ MUX(SCLK_UARTPLL, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
RK2928_CLKSEL_CON(13), 10, 2, MFLAGS),
COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0,
RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
To: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
Subject: [PATCH 3/4] clk: rockchip: assign the SCLK_UARTPLL clock id on rk3036
Date: Tue, 28 Feb 2017 06:14:19 +0100 [thread overview]
Message-ID: <20170228051420.7214-4-heiko@sntech.de> (raw)
In-Reply-To: <20170228051420.7214-1-heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
Assign it to the matching clock in the clock driver.
Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
---
drivers/clk/rockchip/clk-rk3036.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index dcde70f4c105..d10934b63a0d 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -242,7 +242,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(2), 7, 1, MFLAGS,
RK2928_CLKGATE_CON(2), 5, GFLAGS),
- MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
+ MUX(SCLK_UARTPLL, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
RK2928_CLKSEL_CON(13), 10, 2, MFLAGS),
COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0,
RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: heiko@sntech.de (Heiko Stuebner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/4] clk: rockchip: assign the SCLK_UARTPLL clock id on rk3036
Date: Tue, 28 Feb 2017 06:14:19 +0100 [thread overview]
Message-ID: <20170228051420.7214-4-heiko@sntech.de> (raw)
In-Reply-To: <20170228051420.7214-1-heiko@sntech.de>
Assign it to the matching clock in the clock driver.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/clk/rockchip/clk-rk3036.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index dcde70f4c105..d10934b63a0d 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -242,7 +242,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(2), 7, 1, MFLAGS,
RK2928_CLKGATE_CON(2), 5, GFLAGS),
- MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
+ MUX(SCLK_UARTPLL, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
RK2928_CLKSEL_CON(13), 10, 2, MFLAGS),
COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0,
RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
--
2.11.0
next prev parent reply other threads:[~2017-02-28 5:14 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-28 5:14 [PATCH 0/4] rockchip: fix serial output on rk3036 Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` [PATCH 1/4] clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p " Heiko Stuebner
2017-02-28 5:14 ` [PATCH 1/4] clk: rockchip: add ", " " Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 7:33 ` [PATCH 1/4] clk: rockchip: add "," " Stephen Boyd
2017-02-28 7:33 ` Stephen Boyd
2017-02-28 7:33 ` Stephen Boyd
2017-02-28 5:14 ` [PATCH 2/4] clk: rockchip: add SCLK_UARTPLL to rk3036 clock ids Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner [this message]
2017-02-28 5:14 ` [PATCH 3/4] clk: rockchip: assign the SCLK_UARTPLL clock id on rk3036 Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` [PATCH 4/4] ARM: dts: rockchip: Make uartpll a child of the gpll " Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 7:32 ` [PATCH 0/4] rockchip: fix serial output " Stephen Boyd
2017-02-28 7:32 ` Stephen Boyd
2017-02-28 7:32 ` Stephen Boyd
2017-02-28 17:25 ` Heiko Stuebner
2017-02-28 17:25 ` Heiko Stuebner
2017-02-28 17:25 ` Heiko Stuebner
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