From: Heiko Stuebner <heiko@sntech.de>
To: linux-rockchip@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
sboyd@codeaurora.org, mturquette@baylibre.com,
Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH 4/4] ARM: dts: rockchip: Make uartpll a child of the gpll on rk3036
Date: Tue, 28 Feb 2017 06:14:20 +0100 [thread overview]
Message-ID: <20170228051420.7214-5-heiko@sntech.de> (raw)
In-Reply-To: <20170228051420.7214-1-heiko@sntech.de>
The shared uart-pll is normally a child of the apll that can get changed
by cpu frequency scaling. So move it away to the more stable gpll to
make sure the uart doesn't break on cpu frequency changes.
This turned up during the 4.11 merge-window when commit
6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used")
added general termios enablement making the uart on rk3036 change
frequency and thus making it susceptible for the frequency scaling issue.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3036.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index ff9b90bfaefd..6442023854c5 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -310,8 +310,9 @@
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
- assigned-clocks = <&cru PLL_GPLL>;
- assigned-clock-rates = <594000000>;
+ assigned-clocks = <&cru PLL_GPLL>, <&cru SCLK_UARTPLL>;
+ assigned-clock-rates = <594000000>, <0>;
+ assigned-clock-parents = <0>, <&cru PLL_GPLL>;
};
grf: syscon@20008000 {
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
To: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
Subject: [PATCH 4/4] ARM: dts: rockchip: Make uartpll a child of the gpll on rk3036
Date: Tue, 28 Feb 2017 06:14:20 +0100 [thread overview]
Message-ID: <20170228051420.7214-5-heiko@sntech.de> (raw)
In-Reply-To: <20170228051420.7214-1-heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
The shared uart-pll is normally a child of the apll that can get changed
by cpu frequency scaling. So move it away to the more stable gpll to
make sure the uart doesn't break on cpu frequency changes.
This turned up during the 4.11 merge-window when commit
6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used")
added general termios enablement making the uart on rk3036 change
frequency and thus making it susceptible for the frequency scaling issue.
Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
---
arch/arm/boot/dts/rk3036.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index ff9b90bfaefd..6442023854c5 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -310,8 +310,9 @@
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
- assigned-clocks = <&cru PLL_GPLL>;
- assigned-clock-rates = <594000000>;
+ assigned-clocks = <&cru PLL_GPLL>, <&cru SCLK_UARTPLL>;
+ assigned-clock-rates = <594000000>, <0>;
+ assigned-clock-parents = <0>, <&cru PLL_GPLL>;
};
grf: syscon@20008000 {
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: heiko@sntech.de (Heiko Stuebner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/4] ARM: dts: rockchip: Make uartpll a child of the gpll on rk3036
Date: Tue, 28 Feb 2017 06:14:20 +0100 [thread overview]
Message-ID: <20170228051420.7214-5-heiko@sntech.de> (raw)
In-Reply-To: <20170228051420.7214-1-heiko@sntech.de>
The shared uart-pll is normally a child of the apll that can get changed
by cpu frequency scaling. So move it away to the more stable gpll to
make sure the uart doesn't break on cpu frequency changes.
This turned up during the 4.11 merge-window when commit
6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used")
added general termios enablement making the uart on rk3036 change
frequency and thus making it susceptible for the frequency scaling issue.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3036.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index ff9b90bfaefd..6442023854c5 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -310,8 +310,9 @@
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
- assigned-clocks = <&cru PLL_GPLL>;
- assigned-clock-rates = <594000000>;
+ assigned-clocks = <&cru PLL_GPLL>, <&cru SCLK_UARTPLL>;
+ assigned-clock-rates = <594000000>, <0>;
+ assigned-clock-parents = <0>, <&cru PLL_GPLL>;
};
grf: syscon at 20008000 {
--
2.11.0
next prev parent reply other threads:[~2017-02-28 5:14 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-28 5:14 [PATCH 0/4] rockchip: fix serial output on rk3036 Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` [PATCH 1/4] clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p " Heiko Stuebner
2017-02-28 5:14 ` [PATCH 1/4] clk: rockchip: add ", " " Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 7:33 ` [PATCH 1/4] clk: rockchip: add "," " Stephen Boyd
2017-02-28 7:33 ` Stephen Boyd
2017-02-28 7:33 ` Stephen Boyd
2017-02-28 5:14 ` [PATCH 2/4] clk: rockchip: add SCLK_UARTPLL to rk3036 clock ids Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` [PATCH 3/4] clk: rockchip: assign the SCLK_UARTPLL clock id on rk3036 Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner [this message]
2017-02-28 5:14 ` [PATCH 4/4] ARM: dts: rockchip: Make uartpll a child of the gpll " Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 7:32 ` [PATCH 0/4] rockchip: fix serial output " Stephen Boyd
2017-02-28 7:32 ` Stephen Boyd
2017-02-28 7:32 ` Stephen Boyd
2017-02-28 17:25 ` Heiko Stuebner
2017-02-28 17:25 ` Heiko Stuebner
2017-02-28 17:25 ` Heiko Stuebner
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