From: Heiko Stuebner <heiko@sntech.de> To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-rockchip@lists.infradead.org, linux-clk@vger.kernel.org, Heiko Stuebner <heiko@sntech.de> Subject: [PATCH v3 2/2] clk: rockchip: Make uartpll a child of the gpll on rk3036 Date: Wed, 1 Mar 2017 22:00:42 +0100 [thread overview] Message-ID: <20170301210042.11352-3-heiko@sntech.de> (raw) In-Reply-To: <20170301210042.11352-1-heiko@sntech.de> The shared uart-pll is on boot a child of the apll that can get changed by cpu frequency scaling. So move it away to the more stable gpll to make sure the uart doesn't break on cpu frequency changes. This turned up during the 4.11 merge-window when commit 6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used") added general termios enablement making the uart on rk3036 change frequency and thus making it susceptible for the frequency scaling issue. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- drivers/clk/rockchip/clk-rk3036.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index dcde70f4c105..00d4150e33c3 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -450,6 +450,13 @@ static void __init rk3036_clk_init(struct device_node *np) return; } + /* + * Make uart_pll_clk a child of the gpll, as all other sources are + * not that usable / stable. + */ + writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10), + reg_base + RK2928_CLKSEL_CON(13)); + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); if (IS_ERR(ctx)) { pr_err("%s: rockchip clk init failed\n", __func__); -- 2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> To: sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> Subject: [PATCH v3 2/2] clk: rockchip: Make uartpll a child of the gpll on rk3036 Date: Wed, 1 Mar 2017 22:00:42 +0100 [thread overview] Message-ID: <20170301210042.11352-3-heiko@sntech.de> (raw) In-Reply-To: <20170301210042.11352-1-heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> The shared uart-pll is on boot a child of the apll that can get changed by cpu frequency scaling. So move it away to the more stable gpll to make sure the uart doesn't break on cpu frequency changes. This turned up during the 4.11 merge-window when commit 6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used") added general termios enablement making the uart on rk3036 change frequency and thus making it susceptible for the frequency scaling issue. Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> --- drivers/clk/rockchip/clk-rk3036.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index dcde70f4c105..00d4150e33c3 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -450,6 +450,13 @@ static void __init rk3036_clk_init(struct device_node *np) return; } + /* + * Make uart_pll_clk a child of the gpll, as all other sources are + * not that usable / stable. + */ + writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10), + reg_base + RK2928_CLKSEL_CON(13)); + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); if (IS_ERR(ctx)) { pr_err("%s: rockchip clk init failed\n", __func__); -- 2.11.0
next prev parent reply other threads:[~2017-03-01 21:00 UTC|newest] Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-03-01 21:00 [PATCH v3 0/2] rockchip: fix serial output on rk3036 Heiko Stuebner 2017-03-01 21:00 ` Heiko Stuebner 2017-03-01 21:00 ` [PATCH v3 1/2] clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p " Heiko Stuebner 2017-03-01 21:00 ` [PATCH v3 1/2] clk: rockchip: add ", " " Heiko Stuebner 2017-03-01 21:00 ` Heiko Stuebner [this message] 2017-03-01 21:00 ` [PATCH v3 2/2] clk: rockchip: Make uartpll a child of the gpll " Heiko Stuebner 2017-03-07 13:54 ` [PATCH v3 0/2] rockchip: fix serial output " Stephen Boyd 2017-03-07 14:40 ` Heiko Stübner 2017-03-07 14:40 ` Heiko Stübner
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