From: Icenowy Zheng <icenowy@aosc.io>
To: Maxime Ripard <maxime.ripard@free-electrons.com>,
Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,
Icenowy Zheng <icenowy@aosc.xyz>
Subject: [PATCH v4 5/5] arm64: allwinner: a64: add R_PIO pinctrl node
Date: Tue, 4 Apr 2017 17:51:00 +0800 [thread overview]
Message-ID: <20170404095100.18649-6-icenowy@aosc.io> (raw)
In-Reply-To: <20170404095100.18649-1-icenowy@aosc.io>
From: Icenowy Zheng <icenowy@aosc.xyz>
Allwinner A64 have a dedicated pin controller to manage the PL pin bank.
As the driver and the required clock support are added, add the device
node for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1d4e5bcced0c..6bc606b4d74d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -409,5 +409,17 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ r_pio: pinctrl@01f02c00 {
+ compatible = "allwinner,sun50i-a64-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
};
};
--
2.12.2
WARNING: multiple messages have this Message-ID (diff)
From: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
To: Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
Subject: [PATCH v4 5/5] arm64: allwinner: a64: add R_PIO pinctrl node
Date: Tue, 4 Apr 2017 17:51:00 +0800 [thread overview]
Message-ID: <20170404095100.18649-6-icenowy@aosc.io> (raw)
In-Reply-To: <20170404095100.18649-1-icenowy-h8G6r0blFSE@public.gmane.org>
From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
Allwinner A64 have a dedicated pin controller to manage the PL pin bank.
As the driver and the required clock support are added, add the device
node for it.
Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1d4e5bcced0c..6bc606b4d74d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -409,5 +409,17 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ r_pio: pinctrl@01f02c00 {
+ compatible = "allwinner,sun50i-a64-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
};
};
--
2.12.2
WARNING: multiple messages have this Message-ID (diff)
From: Icenowy Zheng <icenowy@aosc.io>
To: Maxime Ripard <maxime.ripard@free-electrons.com>,
Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-sunxi@googlegroups.com, Icenowy Zheng <icenowy@aosc.xyz>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 5/5] arm64: allwinner: a64: add R_PIO pinctrl node
Date: Tue, 4 Apr 2017 17:51:00 +0800 [thread overview]
Message-ID: <20170404095100.18649-6-icenowy@aosc.io> (raw)
In-Reply-To: <20170404095100.18649-1-icenowy@aosc.io>
From: Icenowy Zheng <icenowy@aosc.xyz>
Allwinner A64 have a dedicated pin controller to manage the PL pin bank.
As the driver and the required clock support are added, add the device
node for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1d4e5bcced0c..6bc606b4d74d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -409,5 +409,17 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ r_pio: pinctrl@01f02c00 {
+ compatible = "allwinner,sun50i-a64-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
};
};
--
2.12.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: icenowy@aosc.io (Icenowy Zheng)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 5/5] arm64: allwinner: a64: add R_PIO pinctrl node
Date: Tue, 4 Apr 2017 17:51:00 +0800 [thread overview]
Message-ID: <20170404095100.18649-6-icenowy@aosc.io> (raw)
In-Reply-To: <20170404095100.18649-1-icenowy@aosc.io>
From: Icenowy Zheng <icenowy@aosc.xyz>
Allwinner A64 have a dedicated pin controller to manage the PL pin bank.
As the driver and the required clock support are added, add the device
node for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1d4e5bcced0c..6bc606b4d74d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -409,5 +409,17 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ r_pio: pinctrl at 01f02c00 {
+ compatible = "allwinner,sun50i-a64-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
};
};
--
2.12.2
next prev parent reply other threads:[~2017-04-04 9:53 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-04 9:50 [PATCH v4 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs Icenowy Zheng
2017-04-04 9:50 ` Icenowy Zheng
2017-04-04 9:50 ` Icenowy Zheng
2017-04-04 9:50 ` [PATCH v4 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs Icenowy Zheng
2017-04-04 9:50 ` Icenowy Zheng
2017-04-04 9:50 ` Icenowy Zheng
2017-04-04 9:50 ` Icenowy Zheng
2017-04-04 9:50 ` [PATCH v4 2/5] clk: sunxi-ng: add support for " Icenowy Zheng
2017-04-04 9:50 ` Icenowy Zheng
2017-04-04 9:50 ` Icenowy Zheng
2017-04-04 9:50 ` Icenowy Zheng
2017-04-04 9:50 ` [PATCH v4 3/5] arm64: allwinner: a64: add r_ccu node Icenowy Zheng
2017-04-04 9:50 ` Icenowy Zheng
2017-04-04 9:50 ` Icenowy Zheng
2017-04-04 9:50 ` Icenowy Zheng
2017-04-04 9:50 ` [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu Icenowy Zheng
2017-04-04 9:50 ` Icenowy Zheng
2017-04-04 9:50 ` Icenowy Zheng
2017-04-04 9:50 ` Icenowy Zheng
2017-07-19 22:59 ` [linux-sunxi] " Ondřej Jirman
2017-07-19 22:59 ` Ondřej Jirman
2017-07-19 22:59 ` 'Ondřej Jirman' via linux-sunxi
2017-07-20 2:03 ` [linux-sunxi] " icenowy
2017-07-20 2:03 ` icenowy at aosc.io
2017-07-20 2:03 ` icenowy
2017-07-20 2:03 ` icenowy-h8G6r0blFSE
2017-07-20 2:19 ` [linux-sunxi] " icenowy
2017-07-20 2:19 ` icenowy at aosc.io
2017-07-20 2:19 ` icenowy
2017-07-20 2:19 ` icenowy-h8G6r0blFSE
2017-07-20 5:15 ` [linux-sunxi] " icenowy
2017-07-20 5:15 ` icenowy at aosc.io
2017-07-20 5:15 ` icenowy
2017-07-20 5:15 ` icenowy-h8G6r0blFSE
2017-07-20 8:21 ` [linux-sunxi] " icenowy
2017-07-20 8:21 ` icenowy at aosc.io
2017-07-20 8:21 ` icenowy
2017-07-20 8:21 ` icenowy-h8G6r0blFSE
2017-07-20 12:12 ` [linux-sunxi] " Ondřej Jirman
2017-07-20 12:12 ` Ondřej Jirman
2017-07-20 12:12 ` 'Ondřej Jirman' via linux-sunxi
2017-04-04 9:51 ` Icenowy Zheng [this message]
2017-04-04 9:51 ` [PATCH v4 5/5] arm64: allwinner: a64: add R_PIO pinctrl node Icenowy Zheng
2017-04-04 9:51 ` Icenowy Zheng
2017-04-04 9:51 ` Icenowy Zheng
2017-04-04 15:45 ` [PATCH v4 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs Maxime Ripard
2017-04-04 15:45 ` Maxime Ripard
2017-04-04 15:45 ` Maxime Ripard
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