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From: ville.syrjala@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 04/15] drm/i915: Rename bunch of vlv_ watermark structures to g4x_
Date: Fri, 21 Apr 2017 21:14:21 +0300	[thread overview]
Message-ID: <20170421181432.15216-5-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20170421181432.15216-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We'll be wanting to share some of these watermark structures on g4x,
so let's rename them to have a g4x_ prefix instead of vlv_.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  8 ++++----
 drivers/gpu/drm/i915/intel_drv.h |  6 +++---
 drivers/gpu/drm/i915/intel_pm.c  | 14 +++++++-------
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 357b6c6c2f04..0a393fdc53d1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1760,11 +1760,11 @@ struct ilk_wm_values {
 	enum intel_ddb_partitioning partitioning;
 };
 
-struct vlv_pipe_wm {
+struct g4x_pipe_wm {
 	uint16_t plane[I915_MAX_PLANES];
 };
 
-struct vlv_sr_wm {
+struct g4x_sr_wm {
 	uint16_t plane;
 	uint16_t cursor;
 };
@@ -1774,8 +1774,8 @@ struct vlv_wm_ddl_values {
 };
 
 struct vlv_wm_values {
-	struct vlv_pipe_wm pipe[3];
-	struct vlv_sr_wm sr;
+	struct g4x_pipe_wm pipe[3];
+	struct g4x_sr_wm sr;
 	struct vlv_wm_ddl_values ddl[3];
 	uint8_t level;
 	bool cxsr;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 54f3ff840812..d1cdd10998fa 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -512,8 +512,8 @@ enum vlv_wm_level {
 };
 
 struct vlv_wm_state {
-	struct vlv_pipe_wm wm[NUM_VLV_WM_LEVELS];
-	struct vlv_sr_wm sr[NUM_VLV_WM_LEVELS];
+	struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
+	struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 	uint8_t num_levels;
 	bool cxsr;
 };
@@ -549,7 +549,7 @@ struct intel_crtc_wm_state {
 
 		struct {
 			/* "raw" watermarks (not inverted) */
-			struct vlv_pipe_wm raw[NUM_VLV_WM_LEVELS];
+			struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 			/* intermediate watermarks (inverted) */
 			struct vlv_wm_state intermediate;
 			/* optimal watermarks (inverted) */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ee045be2a5e0..1cc13ccadee6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1062,7 +1062,7 @@ static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	const struct vlv_pipe_wm *raw =
+	const struct g4x_pipe_wm *raw =
 		&crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
 	struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
 	unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
@@ -1178,7 +1178,7 @@ static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
 	bool dirty = false;
 
 	for (; level < num_levels; level++) {
-		struct vlv_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
+		struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
 
 		dirty |= raw->plane[plane_id] != value;
 		raw->plane[plane_id] = value;
@@ -1202,7 +1202,7 @@ static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
 	}
 
 	for (level = 0; level < num_levels; level++) {
-		struct vlv_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
+		struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
 		int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
 		int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
 
@@ -1230,7 +1230,7 @@ static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
 				      enum plane_id plane_id, int level)
 {
-	const struct vlv_pipe_wm *raw =
+	const struct g4x_pipe_wm *raw =
 		&crtc_state->wm.vlv.raw[level];
 	const struct vlv_fifo_state *fifo_state =
 		&crtc_state->wm.vlv.fifo_state;
@@ -1315,7 +1315,7 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 	wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
 
 	for (level = 0; level < wm_state->num_levels; level++) {
-		const struct vlv_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
+		const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
 		const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
 
 		if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
@@ -4785,7 +4785,7 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
 		active->cxsr = wm->cxsr;
 
 		for (level = 0; level < active->num_levels; level++) {
-			struct vlv_pipe_wm *raw =
+			struct g4x_pipe_wm *raw =
 				&crtc_state->wm.vlv.raw[level];
 
 			active->sr[level].plane = wm->sr.plane;
@@ -4845,7 +4845,7 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
 			continue;
 
 		for (level = 0; level < wm_state->num_levels; level++) {
-			struct vlv_pipe_wm *raw =
+			struct g4x_pipe_wm *raw =
 				&crtc_state->wm.vlv.raw[level];
 
 			raw->plane[plane_id] = 0;
-- 
2.10.2

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  parent reply	other threads:[~2017-04-21 18:14 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-21 18:14 [PATCH 00/15] drm/i915: Two stage watermarks for g4x ville.syrjala
2017-04-21 18:14 ` [PATCH 01/15] drm/i915: s/vlv_plane_wm_compute/vlv_raw_plane_wm_compute/ etc ville.syrjala
2017-04-21 18:14 ` [PATCH 02/15] drm/i915: Drop the debug message from vlv_get_fifo_size() ville.syrjala
2017-04-21 18:14 ` [PATCH 03/15] drm/i915: s/vlv_num_wm_levels/intel_wm_num_levels/ ville.syrjala
2017-04-21 18:14 ` ville.syrjala [this message]
2017-04-21 18:14 ` [PATCH 05/15] drm/i915: Make vlv/chv watermark debug print less cryptic ville.syrjala
2017-04-21 18:14 ` [PATCH 06/15] drm/i915: Document CxSR ville.syrjala
2017-04-21 18:14 ` [PATCH 07/15] drm/i915: Fix cursor 'cpp' in watermark calculatins for old platforms ville.syrjala
2017-04-21 18:14 ` [PATCH 08/15] drm/i915: Fix the g4x watermark TLB miss workaround ville.syrjala
2017-04-21 18:14 ` [PATCH 09/15] drm/i915: Refactor the g4x TLB miss w/a to a helper ville.syrjala
2017-04-21 18:14 ` [PATCH 10/15] drm/i915: Refactor wm calculations ville.syrjala
2017-04-21 18:14 ` [PATCH 11/15] drm/i915: Apply the g4x TLB miss w/a to SR watermarks as well ville.syrjala
2017-04-21 18:14 ` [PATCH 12/15] drm/i915: Two stage watermarks for g4x ville.syrjala
2017-04-24  7:34   ` Maarten Lankhorst
2017-04-24 13:16     ` Ville Syrjälä
2017-05-10 16:40     ` Ville Syrjälä
2017-04-21 18:14 ` [PATCH 13/15] drm/i915: Enable HPLL watermarks on g4x ville.syrjala
2017-04-21 18:14 ` [PATCH 14/15] drm/i915: Add g4x watermark tracepoint ville.syrjala
2017-04-21 18:14 ` [PATCH 15/15] drm/i915: Add support for sprites on g4x ville.syrjala
2017-04-21 18:36 ` ✓ Fi.CI.BAT: success for drm/i915: Two stage watermarks for g4x Patchwork
2017-04-24 14:20 ` [PATCH 00/15] " Lofstedt, Marta

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