From: Suman Anna <s-anna@ti.com> To: Tony Lindgren <tony@atomide.com> Cc: devicetree@vger.kernel.org, Lokesh Vutla <lokeshvutla@ti.com>, Tero Kristo <t-kristo@ti.com>, Subhajit Paul <subhajit_paul@ti.com>, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/6] ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock rates Date: Wed, 7 Jun 2017 16:27:26 -0500 [thread overview] Message-ID: <20170607212730.33002-3-s-anna@ti.com> (raw) In-Reply-To: <20170607212730.33002-1-s-anna@ti.com> The IVA DPLL is not an essential DPLL for the functionality of a bootloader and is usually not configured (e.g. older u-boots configure it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer than 2014.01 do not even have an option), and this results in incorrect operating frequencies when trying to use a DSP or IVAHD, whose root clocks are derived from this DPLL. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset values of the dividers H11 & H12 (functional clocks for DSP and IVAHD respectively) are identical to each other, but are different at each OPP. The reset values also do not match a specific OPP. So, the derived output clocks from the IVA DPLL have to be initialized as well to avoid initializing these divider outputs to incorrect frequencies. The clock rates are chosen based on the OPP_NOM values as defined in the OMAP5432 SR2.0 Data Manual Book vK, section 5.2.3.5 "DPLL_IVA Preferred Settings". The recommended maximum DPLL locked frequency is 2330 MHz for OPP_NOM (value for DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of this value. The value 465.92 MHz is used instead of 465.9 MHz for dpll_iva_h11x2_ck so that proper divider value can be calculated. Signed-off-by: Suman Anna <s-anna@ti.com> --- arch/arm/boot/dts/omap54xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 4899c2359d0a..529193442620 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -315,6 +315,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <1165000000>; }; dpll_iva_x2_ck: dpll_iva_x2_ck { @@ -330,6 +332,8 @@ ti,max-div = <63>; reg = <0x01b8>; ti,index-starts-at-one; + assigned-clocks = <&dpll_iva_h11x2_ck>; + assigned-clock-rates = <465920000>; }; dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { @@ -339,6 +343,8 @@ ti,max-div = <63>; reg = <0x01bc>; ti,index-starts-at-one; + assigned-clocks = <&dpll_iva_h12x2_ck>; + assigned-clock-rates = <388300000>; }; mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { -- 2.12.0
WARNING: multiple messages have this Message-ID (diff)
From: s-anna@ti.com (Suman Anna) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/6] ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock rates Date: Wed, 7 Jun 2017 16:27:26 -0500 [thread overview] Message-ID: <20170607212730.33002-3-s-anna@ti.com> (raw) In-Reply-To: <20170607212730.33002-1-s-anna@ti.com> The IVA DPLL is not an essential DPLL for the functionality of a bootloader and is usually not configured (e.g. older u-boots configure it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer than 2014.01 do not even have an option), and this results in incorrect operating frequencies when trying to use a DSP or IVAHD, whose root clocks are derived from this DPLL. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset values of the dividers H11 & H12 (functional clocks for DSP and IVAHD respectively) are identical to each other, but are different at each OPP. The reset values also do not match a specific OPP. So, the derived output clocks from the IVA DPLL have to be initialized as well to avoid initializing these divider outputs to incorrect frequencies. The clock rates are chosen based on the OPP_NOM values as defined in the OMAP5432 SR2.0 Data Manual Book vK, section 5.2.3.5 "DPLL_IVA Preferred Settings". The recommended maximum DPLL locked frequency is 2330 MHz for OPP_NOM (value for DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of this value. The value 465.92 MHz is used instead of 465.9 MHz for dpll_iva_h11x2_ck so that proper divider value can be calculated. Signed-off-by: Suman Anna <s-anna@ti.com> --- arch/arm/boot/dts/omap54xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 4899c2359d0a..529193442620 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -315,6 +315,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <1165000000>; }; dpll_iva_x2_ck: dpll_iva_x2_ck { @@ -330,6 +332,8 @@ ti,max-div = <63>; reg = <0x01b8>; ti,index-starts-at-one; + assigned-clocks = <&dpll_iva_h11x2_ck>; + assigned-clock-rates = <465920000>; }; dpll_iva_h12x2_ck: dpll_iva_h12x2_ck at 1bc { @@ -339,6 +343,8 @@ ti,max-div = <63>; reg = <0x01bc>; ti,index-starts-at-one; + assigned-clocks = <&dpll_iva_h12x2_ck>; + assigned-clock-rates = <388300000>; }; mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { -- 2.12.0
next prev parent reply other threads:[~2017-06-07 21:27 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-06-07 21:27 [PATCH 0/6] Init Clock frequences for accelerators Suman Anna 2017-06-07 21:27 ` Suman Anna 2017-06-07 21:27 ` Suman Anna [this message] 2017-06-07 21:27 ` [PATCH 2/6] ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock rates Suman Anna 2017-06-07 21:27 ` [PATCH 4/6] ARM: dts: dra7xx-clocks: Set DSP " Suman Anna 2017-06-07 21:27 ` Suman Anna [not found] ` <20170607212730.33002-1-s-anna-l0cyMroinI0@public.gmane.org> 2017-06-07 21:27 ` [PATCH 1/6] ARM: dts: omap44xx-clocks: Set IVA " Suman Anna 2017-06-07 21:27 ` Suman Anna 2017-06-07 21:27 ` [PATCH 3/6] ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL Suman Anna 2017-06-07 21:27 ` Suman Anna 2017-06-07 21:27 ` [PATCH 5/6] ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock rates Suman Anna 2017-06-07 21:27 ` Suman Anna 2017-06-07 21:27 ` [PATCH 6/6] ARM: dts: dra7xx-clocks: Use DPLL_GPU for GPU clocks Suman Anna 2017-06-07 21:27 ` Suman Anna 2017-06-12 7:36 ` [PATCH 0/6] Init Clock frequences for accelerators Tony Lindgren 2017-06-12 7:36 ` Tony Lindgren 2017-06-12 8:32 ` Tero Kristo 2017-06-12 8:32 ` Tero Kristo [not found] ` <ea1b56dd-1a91-42a1-6247-2acd0dcc1dab-l0cyMroinI0@public.gmane.org> 2017-06-12 10:06 ` Tony Lindgren 2017-06-12 10:06 ` Tony Lindgren
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