From: Suman Anna <s-anna@ti.com> To: Tony Lindgren <tony@atomide.com> Cc: devicetree@vger.kernel.org, Lokesh Vutla <lokeshvutla@ti.com>, Tero Kristo <t-kristo@ti.com>, Subhajit Paul <subhajit_paul@ti.com>, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/6] ARM: dts: dra7xx-clocks: Set DSP DPLL and its output clock rates Date: Wed, 7 Jun 2017 16:27:28 -0500 [thread overview] Message-ID: <20170607212730.33002-5-s-anna@ti.com> (raw) In-Reply-To: <20170607212730.33002-1-s-anna@ti.com> The DSP DPLL is a new DPLL compared to previous OMAP generations and supplies the root clocks for the DSP processors, as well as a mux input source for EVE sub-system (on applicable SoCs). This DPLL is currently not configured by older bootloaders. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the DSP DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL and be independent of the bootloader version. Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The DSP DPLL provides two output clocks, DSP_GFCLK and EVE_GCLK. The desired rate for DSP_GFCLK is 600 MHz (same as DSP DPLL CLKOUT frequency), and is currently auto set due to the desired M2 divider value being the same as reset value for the locked frequency of 600 MHz. The EVE_GCLK however is required to be 400 MHz, so set the dpll_dsp_m3x2_ck's rate explicitly so that the divider is set properly. The dpll_dsp_m2_ck rate is also set explicitly to not rely on any implicit matching divider reset values to the locked DPLL frequency. The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The clock rates are chosen based on these OPP_NOM values and defined as per a DRA7xx PLL spec document. The DPLL locked frequency is 1200 MHz, so the dpll_dsp_ck clock rate used is half of this value. Signed-off-by: Suman Anna <s-anna@ti.com> --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index cfaf27215901..8a82490035d9 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -338,6 +338,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; + assigned-clocks = <&dpll_dsp_ck>; + assigned-clock-rates = <600000000>; }; dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { @@ -349,6 +351,8 @@ reg = <0x0244>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m2_ck>; + assigned-clock-rates = <600000000>; }; iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { @@ -659,6 +663,8 @@ reg = <0x0248>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m3x2_ck>; + assigned-clock-rates = <400000000>; }; dpll_gmac_x2_ck: dpll_gmac_x2_ck { -- 2.12.0
WARNING: multiple messages have this Message-ID (diff)
From: s-anna@ti.com (Suman Anna) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/6] ARM: dts: dra7xx-clocks: Set DSP DPLL and its output clock rates Date: Wed, 7 Jun 2017 16:27:28 -0500 [thread overview] Message-ID: <20170607212730.33002-5-s-anna@ti.com> (raw) In-Reply-To: <20170607212730.33002-1-s-anna@ti.com> The DSP DPLL is a new DPLL compared to previous OMAP generations and supplies the root clocks for the DSP processors, as well as a mux input source for EVE sub-system (on applicable SoCs). This DPLL is currently not configured by older bootloaders. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the DSP DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL and be independent of the bootloader version. Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The DSP DPLL provides two output clocks, DSP_GFCLK and EVE_GCLK. The desired rate for DSP_GFCLK is 600 MHz (same as DSP DPLL CLKOUT frequency), and is currently auto set due to the desired M2 divider value being the same as reset value for the locked frequency of 600 MHz. The EVE_GCLK however is required to be 400 MHz, so set the dpll_dsp_m3x2_ck's rate explicitly so that the divider is set properly. The dpll_dsp_m2_ck rate is also set explicitly to not rely on any implicit matching divider reset values to the locked DPLL frequency. The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The clock rates are chosen based on these OPP_NOM values and defined as per a DRA7xx PLL spec document. The DPLL locked frequency is 1200 MHz, so the dpll_dsp_ck clock rate used is half of this value. Signed-off-by: Suman Anna <s-anna@ti.com> --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index cfaf27215901..8a82490035d9 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -338,6 +338,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; + assigned-clocks = <&dpll_dsp_ck>; + assigned-clock-rates = <600000000>; }; dpll_dsp_m2_ck: dpll_dsp_m2_ck at 244 { @@ -349,6 +351,8 @@ reg = <0x0244>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m2_ck>; + assigned-clock-rates = <600000000>; }; iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { @@ -659,6 +663,8 @@ reg = <0x0248>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m3x2_ck>; + assigned-clock-rates = <400000000>; }; dpll_gmac_x2_ck: dpll_gmac_x2_ck { -- 2.12.0
next prev parent reply other threads:[~2017-06-07 21:27 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-06-07 21:27 [PATCH 0/6] Init Clock frequences for accelerators Suman Anna 2017-06-07 21:27 ` Suman Anna 2017-06-07 21:27 ` [PATCH 2/6] ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock rates Suman Anna 2017-06-07 21:27 ` Suman Anna 2017-06-07 21:27 ` Suman Anna [this message] 2017-06-07 21:27 ` [PATCH 4/6] ARM: dts: dra7xx-clocks: Set DSP " Suman Anna [not found] ` <20170607212730.33002-1-s-anna-l0cyMroinI0@public.gmane.org> 2017-06-07 21:27 ` [PATCH 1/6] ARM: dts: omap44xx-clocks: Set IVA " Suman Anna 2017-06-07 21:27 ` Suman Anna 2017-06-07 21:27 ` [PATCH 3/6] ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL Suman Anna 2017-06-07 21:27 ` Suman Anna 2017-06-07 21:27 ` [PATCH 5/6] ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock rates Suman Anna 2017-06-07 21:27 ` Suman Anna 2017-06-07 21:27 ` [PATCH 6/6] ARM: dts: dra7xx-clocks: Use DPLL_GPU for GPU clocks Suman Anna 2017-06-07 21:27 ` Suman Anna 2017-06-12 7:36 ` [PATCH 0/6] Init Clock frequences for accelerators Tony Lindgren 2017-06-12 7:36 ` Tony Lindgren 2017-06-12 8:32 ` Tero Kristo 2017-06-12 8:32 ` Tero Kristo [not found] ` <ea1b56dd-1a91-42a1-6247-2acd0dcc1dab-l0cyMroinI0@public.gmane.org> 2017-06-12 10:06 ` Tony Lindgren 2017-06-12 10:06 ` Tony Lindgren
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