From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v3 11/30] target/sh4: Unify cpu_fregs into FREG
Date: Tue, 18 Jul 2017 10:02:36 -1000 [thread overview]
Message-ID: <20170718200255.31647-12-rth@twiddle.net> (raw)
In-Reply-To: <20170718200255.31647-1-rth@twiddle.net>
We were treating FREG as an index and REG as a TCGv.
Making FREG return a TCGv is both less confusing and
a step toward cleaner banking of cpu_fregs.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/sh4/translate.c | 125 ++++++++++++++++++++-----------------------------
1 file changed, 52 insertions(+), 73 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index ef6f674..b3c3e8e 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -359,10 +359,11 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
#define REG(x) cpu_gregs[(x) ^ ctx->gbank]
#define ALTREG(x) cpu_gregs[(x) ^ ctx->gbank ^ 0x10]
-#define FREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x))
+#define FREG(x) cpu_fregs[ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)]
#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
-#define XREG(x) (ctx->tbflags & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
-#define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
+#define XREG(x) FREG(XHACK(x))
+/* Assumes lsb of (x) is always 0 */
+#define DREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x))
#define CHECK_NOT_DELAY_SLOT \
if (ctx->envflags & DELAY_SLOT_MASK) { \
@@ -983,56 +984,51 @@ static void _decode_opc(DisasContext * ctx)
CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_SZ) {
TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- gen_store_fpr64(fp, XREG(B11_8));
+ gen_load_fpr64(fp, XHACK(B7_4));
+ gen_store_fpr64(fp, XHACK(B11_8));
tcg_temp_free_i64(fp);
} else {
- tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
+ tcg_gen_mov_i32(FREG(B11_8), FREG(B7_4));
}
return;
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_SZ) {
TCGv addr_hi = tcg_temp_new();
- int fr = XREG(B7_4);
+ int fr = XHACK(B7_4);
tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
- tcg_gen_qemu_st_i32(cpu_fregs[fr], REG(B11_8),
- ctx->memidx, MO_TEUL);
- tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr_hi,
- ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(FREG(fr), REG(B11_8), ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL);
tcg_temp_free(addr_hi);
} else {
- tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], REG(B11_8),
- ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL);
}
return;
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_SZ) {
TCGv addr_hi = tcg_temp_new();
- int fr = XREG(B11_8);
+ int fr = XHACK(B11_8);
tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
- tcg_gen_qemu_ld_i32(cpu_fregs[fr], REG(B7_4), ctx->memidx, MO_TEUL);
- tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr_hi, ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL);
tcg_temp_free(addr_hi);
} else {
- tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], REG(B7_4),
- ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TEUL);
}
return;
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_SZ) {
TCGv addr_hi = tcg_temp_new();
- int fr = XREG(B11_8);
+ int fr = XHACK(B11_8);
tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
- tcg_gen_qemu_ld_i32(cpu_fregs[fr], REG(B7_4), ctx->memidx, MO_TEUL);
- tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr_hi, ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
tcg_temp_free(addr_hi);
} else {
- tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], REG(B7_4),
- ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TEUL);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
}
return;
@@ -1041,13 +1037,12 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new_i32();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
if (ctx->tbflags & FPSCR_SZ) {
- int fr = XREG(B7_4);
- tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr, ctx->memidx, MO_TEUL);
+ int fr = XHACK(B7_4);
+ tcg_gen_qemu_st_i32(FREG(fr + 1), addr, ctx->memidx, MO_TEUL);
tcg_gen_subi_i32(addr, addr, 4);
- tcg_gen_qemu_st_i32(cpu_fregs[fr], addr, ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(FREG(fr), addr, ctx->memidx, MO_TEUL);
} else {
- tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], addr,
- ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL);
}
tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
@@ -1058,15 +1053,12 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new_i32();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
if (ctx->tbflags & FPSCR_SZ) {
- int fr = XREG(B11_8);
- tcg_gen_qemu_ld_i32(cpu_fregs[fr], addr,
- ctx->memidx, MO_TEUL);
+ int fr = XHACK(B11_8);
+ tcg_gen_qemu_ld_i32(FREG(fr), addr, ctx->memidx, MO_TEUL);
tcg_gen_addi_i32(addr, addr, 4);
- tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr,
- ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_ld_i32(FREG(fr + 1), addr, ctx->memidx, MO_TEUL);
} else {
- tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], addr,
- ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_ld_i32(FREG(B11_8), addr, ctx->memidx, MO_TEUL);
}
tcg_temp_free(addr);
}
@@ -1077,15 +1069,12 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
if (ctx->tbflags & FPSCR_SZ) {
- int fr = XREG(B7_4);
- tcg_gen_qemu_ld_i32(cpu_fregs[fr], addr,
- ctx->memidx, MO_TEUL);
+ int fr = XHACK(B7_4);
+ tcg_gen_qemu_ld_i32(FREG(fr), addr, ctx->memidx, MO_TEUL);
tcg_gen_addi_i32(addr, addr, 4);
- tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr,
- ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_ld_i32(FREG(fr + 1), addr, ctx->memidx, MO_TEUL);
} else {
- tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], addr,
- ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL);
}
tcg_temp_free(addr);
}
@@ -1133,34 +1122,28 @@ static void _decode_opc(DisasContext * ctx)
} else {
switch (ctx->opcode & 0xf00f) {
case 0xf000: /* fadd Rm,Rn */
- gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_env,
- cpu_fregs[FREG(B11_8)],
- cpu_fregs[FREG(B7_4)]);
+ gen_helper_fadd_FT(FREG(B11_8), cpu_env,
+ FREG(B11_8), FREG(B7_4));
break;
case 0xf001: /* fsub Rm,Rn */
- gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_env,
- cpu_fregs[FREG(B11_8)],
- cpu_fregs[FREG(B7_4)]);
+ gen_helper_fsub_FT(FREG(B11_8), cpu_env,
+ FREG(B11_8), FREG(B7_4));
break;
case 0xf002: /* fmul Rm,Rn */
- gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_env,
- cpu_fregs[FREG(B11_8)],
- cpu_fregs[FREG(B7_4)]);
+ gen_helper_fmul_FT(FREG(B11_8), cpu_env,
+ FREG(B11_8), FREG(B7_4));
break;
case 0xf003: /* fdiv Rm,Rn */
- gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_env,
- cpu_fregs[FREG(B11_8)],
- cpu_fregs[FREG(B7_4)]);
+ gen_helper_fdiv_FT(FREG(B11_8), cpu_env,
+ FREG(B11_8), FREG(B7_4));
break;
case 0xf004: /* fcmp/eq Rm,Rn */
gen_helper_fcmp_eq_FT(cpu_sr_t, cpu_env,
- cpu_fregs[FREG(B11_8)],
- cpu_fregs[FREG(B7_4)]);
+ FREG(B11_8), FREG(B7_4));
return;
case 0xf005: /* fcmp/gt Rm,Rn */
gen_helper_fcmp_gt_FT(cpu_sr_t, cpu_env,
- cpu_fregs[FREG(B11_8)],
- cpu_fregs[FREG(B7_4)]);
+ FREG(B11_8), FREG(B7_4));
return;
}
}
@@ -1172,9 +1155,8 @@ static void _decode_opc(DisasContext * ctx)
if (ctx->tbflags & FPSCR_PR) {
break; /* illegal instruction */
} else {
- gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)], cpu_env,
- cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)],
- cpu_fregs[FREG(B11_8)]);
+ gen_helper_fmac_FT(FREG(B11_8), cpu_env,
+ FREG(0), FREG(B7_4), FREG(B11_8));
return;
}
}
@@ -1705,11 +1687,11 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
CHECK_FPU_ENABLED
- tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul);
+ tcg_gen_mov_i32(FREG(B11_8), cpu_fpul);
return;
case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
CHECK_FPU_ENABLED
- tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]);
+ tcg_gen_mov_i32(cpu_fpul, FREG(B11_8));
return;
case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
CHECK_FPU_ENABLED
@@ -1723,7 +1705,7 @@ static void _decode_opc(DisasContext * ctx)
tcg_temp_free_i64(fp);
}
else {
- gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_env, cpu_fpul);
+ gen_helper_float_FT(FREG(B11_8), cpu_env, cpu_fpul);
}
return;
case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
@@ -1738,18 +1720,16 @@ static void _decode_opc(DisasContext * ctx)
tcg_temp_free_i64(fp);
}
else {
- gen_helper_ftrc_FT(cpu_fpul, cpu_env, cpu_fregs[FREG(B11_8)]);
+ gen_helper_ftrc_FT(cpu_fpul, cpu_env, FREG(B11_8));
}
return;
case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
CHECK_FPU_ENABLED
- tcg_gen_xori_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)],
- 0x80000000);
+ tcg_gen_xori_i32(FREG(B11_8), FREG(B11_8), 0x80000000);
return;
case 0xf05d: /* fabs FRn/DRn - FPCSR: Nothing */
CHECK_FPU_ENABLED
- tcg_gen_andi_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)],
- 0x7fffffff);
+ tcg_gen_andi_i32(FREG(B11_8), FREG(B11_8), 0x7fffffff);
return;
case 0xf06d: /* fsqrt FRn */
CHECK_FPU_ENABLED
@@ -1762,8 +1742,7 @@ static void _decode_opc(DisasContext * ctx)
gen_store_fpr64(fp, DREG(B11_8));
tcg_temp_free_i64(fp);
} else {
- gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_env,
- cpu_fregs[FREG(B11_8)]);
+ gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8));
}
return;
case 0xf07d: /* fsrra FRn */
@@ -1772,13 +1751,13 @@ static void _decode_opc(DisasContext * ctx)
case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
CHECK_FPU_ENABLED
if (!(ctx->tbflags & FPSCR_PR)) {
- tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
+ tcg_gen_movi_i32(FREG(B11_8), 0);
}
return;
case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
CHECK_FPU_ENABLED
if (!(ctx->tbflags & FPSCR_PR)) {
- tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
+ tcg_gen_movi_i32(FREG(B11_8), 0x3f800000);
}
return;
case 0xf0ad: /* fcnvsd FPUL,DRn */
--
2.9.4
next prev parent reply other threads:[~2017-07-18 20:04 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-18 20:02 [Qemu-devel] [PATCH v3 00/30] target/sh4 improvements Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 01/30] target/sh4: Use cmpxchg for movco Richard Henderson
2017-07-18 20:19 ` Aurelien Jarno
2017-07-18 21:36 ` Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 02/30] target/sh4: Consolidate end-of-TB tests Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 03/30] target/sh4: Introduce TB_FLAG_ENVFLAGS_MASK Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 04/30] target/sh4: Keep env->flags clean Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 05/30] target/sh4: Adjust TB_FLAG_PENDING_MOVCA Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 06/30] target/sh4: Handle user-space atomics Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 07/30] target/sh4: Recognize common gUSA sequences Richard Henderson
2017-07-18 20:32 ` Aurelien Jarno
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 08/30] linux-user/sh4: Notice gUSA regions during signal delivery Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 09/30] linux-user/sh4: Clean env->flags on signal boundaries Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 10/30] target/sh4: Hoist register bank selection Richard Henderson
2017-07-18 20:02 ` Richard Henderson [this message]
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 12/30] target/sh4: Pass DisasContext to fpr64 routines Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 14/30] target/sh4: Eliminate unused XREG macro Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 15/30] target/sh4: Merge DREG into fpr64 routines Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 16/30] target/sh4: Load/store Dr as 64-bit quantities Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 17/30] target/sh4: Simplify 64-bit fp reg-reg move Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 18/30] target/sh4: Unify code for CHECK_NOT_DELAY_SLOT Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 19/30] target/sh4: Unify code for CHECK_PRIVILEGED Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 20/30] target/sh4: Unify code for CHECK_FPU_ENABLED Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 21/30] target/sh4: Tidy misc illegal insn checks Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 22/30] target/sh4: Introduce CHECK_FPSCR_PR_* Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 23/30] target/sh4: Introduce CHECK_SH4A Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 24/30] target/sh4: Implement fpchg Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 25/30] target/sh4: Add missing FPSCR.PR == 0 checks Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 26/30] target/sh4: Implement fsrra Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 27/30] target/sh4: Use tcg_gen_lookup_and_goto_ptr Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 28/30] tcg: Fix off-by-one in assert in page_set_flags Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 29/30] linux-user: Tidy and enforce reserved_va initialization Richard Henderson
2017-07-18 20:02 ` [Qemu-devel] [PATCH v3 30/30] linux-user/sh4: Reduce TARGET_VIRT_ADDR_SPACE_BITS to 31 Richard Henderson
2017-07-18 21:02 ` [Qemu-devel] [PATCH v3 00/30] target/sh4 improvements Aurelien Jarno
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