From: Dietmar Eggemann <dietmar.eggemann@arm.com> To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: Russell King <linux@armlinux.org.uk>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Kukjin Kim <kgene@kernel.org>, Krzysztof Kozlowski <krzk@kernel.org>, Vincent Guittot <vincent.guittot@linaro.org>, Juri Lelli <juri.lelli@arm.com> Subject: [PATCH 4/4] arm: dts: r8a7790: add cpu capacity-dmips-mhz information Date: Wed, 30 Aug 2017 15:41:20 +0100 [thread overview] Message-ID: <20170830144120.9312-5-dietmar.eggemann@arm.com> (raw) In-Reply-To: <20170830144120.9312-1-dietmar.eggemann@arm.com> The following 'capacity-dmips-mhz' dt property values are used: Cortex-A15: 1024, Cortex-A7: 539 They have been derived form the cpu_efficiency values: Cortex-A15: 3891, Cortex-A7: 2048 by scaling them so that the Cortex-A15s (big cores) use 1024. The cpu_efficiency values were originally derived from the "Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7" white paper (http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x (3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the Dhrystone benchmark. The following platform is affected once cpu-invariant accounting support is re-connected to the task scheduler: r8a7790-lager Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com> --- arch/arm/boot/dts/r8a7790.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 2805a8608d4b..a57c0e170d8b 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -56,6 +56,7 @@ clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7790_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; /* kHz - uV - OPPs unknown yet */ operating-points = <1400000 1000000>, @@ -73,6 +74,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu2: cpu@2 { @@ -82,6 +84,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu3: cpu@3 { @@ -91,6 +94,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu4: cpu@100 { @@ -100,6 +104,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU0>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu5: cpu@101 { @@ -109,6 +114,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu6: cpu@102 { @@ -118,6 +124,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU2>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu7: cpu@103 { @@ -127,6 +134,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU3>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; L2_CA15: cache-controller-0 { -- 2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: dietmar.eggemann@arm.com (Dietmar Eggemann) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/4] arm: dts: r8a7790: add cpu capacity-dmips-mhz information Date: Wed, 30 Aug 2017 15:41:20 +0100 [thread overview] Message-ID: <20170830144120.9312-5-dietmar.eggemann@arm.com> (raw) In-Reply-To: <20170830144120.9312-1-dietmar.eggemann@arm.com> The following 'capacity-dmips-mhz' dt property values are used: Cortex-A15: 1024, Cortex-A7: 539 They have been derived form the cpu_efficiency values: Cortex-A15: 3891, Cortex-A7: 2048 by scaling them so that the Cortex-A15s (big cores) use 1024. The cpu_efficiency values were originally derived from the "Big.LITTLE Processing with ARM Cortex?-A15 & Cortex-A7" white paper (http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x (3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the Dhrystone benchmark. The following platform is affected once cpu-invariant accounting support is re-connected to the task scheduler: r8a7790-lager Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com> --- arch/arm/boot/dts/r8a7790.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 2805a8608d4b..a57c0e170d8b 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -56,6 +56,7 @@ clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7790_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; /* kHz - uV - OPPs unknown yet */ operating-points = <1400000 1000000>, @@ -73,6 +74,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu2: cpu at 2 { @@ -82,6 +84,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu3: cpu at 3 { @@ -91,6 +94,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu4: cpu at 100 { @@ -100,6 +104,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU0>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu5: cpu at 101 { @@ -109,6 +114,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu6: cpu at 102 { @@ -118,6 +124,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU2>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu7: cpu at 103 { @@ -127,6 +134,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU3>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; L2_CA15: cache-controller-0 { -- 2.11.0
next prev parent reply other threads:[~2017-08-30 14:41 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-08-30 14:41 [PATCH 0/4] arm: remove cpu_efficiency Dietmar Eggemann 2017-08-30 14:41 ` Dietmar Eggemann 2017-08-30 14:41 ` [PATCH 1/4] arm: topology: " Dietmar Eggemann 2017-08-30 14:41 ` Dietmar Eggemann 2017-09-04 7:49 ` Vincent Guittot 2017-09-04 7:49 ` Vincent Guittot 2017-09-04 7:49 ` Vincent Guittot 2017-09-06 11:43 ` Dietmar Eggemann 2017-09-06 11:43 ` Dietmar Eggemann 2017-09-06 12:40 ` Vincent Guittot 2017-09-06 12:40 ` Vincent Guittot 2017-09-06 12:40 ` Vincent Guittot 2017-09-07 10:41 ` Dietmar Eggemann 2017-09-07 10:41 ` Dietmar Eggemann 2017-08-30 14:41 ` [PATCH 2/4] arm: dts: exynos: add exynos5420 cpu capacity-dmips-mhz information Dietmar Eggemann 2017-08-30 14:41 ` Dietmar Eggemann 2017-08-30 14:41 ` Dietmar Eggemann 2017-08-30 20:26 ` Krzysztof Kozlowski 2017-08-30 20:26 ` Krzysztof Kozlowski 2017-08-30 20:26 ` Krzysztof Kozlowski 2017-08-31 10:36 ` Dietmar Eggemann 2017-08-31 10:36 ` Dietmar Eggemann 2017-09-03 19:56 ` Krzysztof Kozlowski 2017-09-03 19:56 ` Krzysztof Kozlowski 2017-09-06 11:47 ` Dietmar Eggemann 2017-09-06 11:47 ` Dietmar Eggemann 2017-09-06 11:47 ` Dietmar Eggemann 2017-09-17 7:37 ` Krzysztof Kozlowski 2017-09-17 7:37 ` Krzysztof Kozlowski 2017-08-30 14:41 ` [PATCH 3/4] arm: dts: exynos: add exynos5422 " Dietmar Eggemann 2017-08-30 14:41 ` Dietmar Eggemann 2017-08-30 14:41 ` Dietmar Eggemann 2017-09-17 7:37 ` Krzysztof Kozlowski 2017-09-17 7:37 ` Krzysztof Kozlowski 2017-08-30 14:41 ` Dietmar Eggemann [this message] 2017-08-30 14:41 ` [PATCH 4/4] arm: dts: r8a7790: add " Dietmar Eggemann 2017-09-18 7:39 ` Simon Horman 2017-09-18 7:39 ` Simon Horman 2017-10-09 17:55 ` Dietmar Eggemann 2017-10-09 17:55 ` Dietmar Eggemann
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20170830144120.9312-5-dietmar.eggemann@arm.com \ --to=dietmar.eggemann@arm.com \ --cc=devicetree@vger.kernel.org \ --cc=juri.lelli@arm.com \ --cc=kgene@kernel.org \ --cc=krzk@kernel.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-renesas-soc@vger.kernel.org \ --cc=linux-samsung-soc@vger.kernel.org \ --cc=linux@armlinux.org.uk \ --cc=mark.rutland@arm.com \ --cc=robh+dt@kernel.org \ --cc=vincent.guittot@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.