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From: Stafford Horne <shorne@gmail.com>
To: QEMU Development <qemu-devel@nongnu.org>
Cc: Richard Henderson <rth@twiddle.net>,
	Richard Henderson <richard.henderson@linaro.org>,
	Openrisc <openrisc@lists.librecores.org>,
	Stafford Horne <shorne@gmail.com>
Subject: [Qemu-devel] [PATCH v2 2/5] target/openrisc: Make coreid and numcores variable
Date: Fri, 13 Oct 2017 22:49:27 +0900	[thread overview]
Message-ID: <20171013134930.32547-3-shorne@gmail.com> (raw)
In-Reply-To: <20171013134930.32547-1-shorne@gmail.com>

Previously coreid and numcores were hard coded as 0 and 1 respectively
as OpenRISC QEMU did not have multicore support.

Multicore support is now being added so these registers need to have
configured values.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 target/openrisc/sys_helper.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index abdef5d6a5..dc6e5cc7f2 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -23,6 +23,7 @@
 #include "exec/exec-all.h"
 #include "exec/helper-proto.h"
 #include "exception.h"
+#include "sysemu/sysemu.h"
 
 #define TO_SPR(group, number) (((group) << 11) + (number))
 
@@ -249,10 +250,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
         return env->esr;
 
     case TO_SPR(0, 128): /* COREID */
-        return 0;
+        return cpu->parent_obj.cpu_index;
 
     case TO_SPR(0, 129): /* NUMCORES */
-        return 1;
+        return max_cpus;
 
     case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
         idx = (spr - 1024);
-- 
2.13.6

WARNING: multiple messages have this Message-ID (diff)
From: Stafford Horne <shorne@gmail.com>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH v2 2/5] target/openrisc: Make coreid and numcores variable
Date: Fri, 13 Oct 2017 22:49:27 +0900	[thread overview]
Message-ID: <20171013134930.32547-3-shorne@gmail.com> (raw)
In-Reply-To: <20171013134930.32547-1-shorne@gmail.com>

Previously coreid and numcores were hard coded as 0 and 1 respectively
as OpenRISC QEMU did not have multicore support.

Multicore support is now being added so these registers need to have
configured values.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 target/openrisc/sys_helper.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index abdef5d6a5..dc6e5cc7f2 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -23,6 +23,7 @@
 #include "exec/exec-all.h"
 #include "exec/helper-proto.h"
 #include "exception.h"
+#include "sysemu/sysemu.h"
 
 #define TO_SPR(group, number) (((group) << 11) + (number))
 
@@ -249,10 +250,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
         return env->esr;
 
     case TO_SPR(0, 128): /* COREID */
-        return 0;
+        return cpu->parent_obj.cpu_index;
 
     case TO_SPR(0, 129): /* NUMCORES */
-        return 1;
+        return max_cpus;
 
     case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
         idx = (spr - 1024);
-- 
2.13.6


  parent reply	other threads:[~2017-10-13 13:49 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-13 13:49 [Qemu-devel] [PATCH v2 0/5] OpenRISC SMP Support Stafford Horne
2017-10-13 13:49 ` [OpenRISC] " Stafford Horne
2017-10-13 13:49 ` [Qemu-devel] [PATCH v2 1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC) Stafford Horne
2017-10-13 13:49   ` [OpenRISC] " Stafford Horne
2017-10-13 13:49 ` Stafford Horne [this message]
2017-10-13 13:49   ` [OpenRISC] [PATCH v2 2/5] target/openrisc: Make coreid and numcores variable Stafford Horne
2017-10-13 13:58   ` [Qemu-devel] " Richard Henderson
2017-10-13 13:58     ` [OpenRISC] " Richard Henderson
2017-10-13 14:31     ` [Qemu-devel] " Stafford Horne
2017-10-13 14:31       ` [OpenRISC] " Stafford Horne
2017-10-13 13:49 ` [Qemu-devel] [PATCH v2 3/5] openrisc/cputimer: Perparation for Multicore Stafford Horne
2017-10-13 13:49   ` [OpenRISC] " Stafford Horne
2017-10-13 13:49 ` [Qemu-devel] [PATCH v2 4/5] openrisc: Initial SMP support Stafford Horne
2017-10-13 13:49   ` [OpenRISC] " Stafford Horne
2017-10-13 13:49 ` [Qemu-devel] [PATCH v2 5/5] openrisc: Only kick cpu on timeout, not on update Stafford Horne
2017-10-13 13:49   ` [OpenRISC] " Stafford Horne

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