From: Joel Stanley <joel@jms.id.au> To: Lee Jones <lee.jones@linaro.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@codeaurora.org> Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery <andrew@aj.id.au>, Benjamin Herrenschmidt <benh@kernel.crashing.org>, Jeremy Kerr <jk@ozlabs.org>, Rick Altherr <raltherr@google.com>, Ryan Chen <ryan_chen@aspeedtech.com>, Arnd Bergmann <arnd@arndb.de> Subject: [PATCH v5 5/5] clk: aspeed: Add reset controller Date: Mon, 30 Oct 2017 16:32:50 +1030 [thread overview] Message-ID: <20171030060250.701-6-joel@jms.id.au> (raw) In-Reply-To: <20171030060250.701-1-joel@jms.id.au> There are some resets that are not associated with gates. These are represented by a reset controller. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> --- v5: - Add Andrew's Reviewed-by v3: - Add named initalisers for the reset defines - Add define for ADC --- drivers/clk/clk-aspeed.c | 82 +++++++++++++++++++++++++++++++- include/dt-bindings/clock/aspeed-clock.h | 10 ++++ 2 files changed, 91 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index df5bc57a6ee2..d91e86c70e0c 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -17,6 +17,7 @@ #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> +#include <linux/reset-controller.h> #include <linux/slab.h> #include <linux/spinlock.h> @@ -275,6 +276,68 @@ static const struct clk_ops aspeed_clk_gate_ops = { .is_enabled = aspeed_clk_is_enabled, }; +/** + * struct aspeed_reset - Aspeed reset controller + * @map: regmap to access the containing system controller + * @rcdev: reset controller device + */ +struct aspeed_reset { + struct regmap *map; + struct reset_controller_dev rcdev; +}; + +#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) + +static const u8 aspeed_resets[] = { + [ASPEED_RESET_XDMA] = 25, + [ASPEED_RESET_MCTP] = 24, + [ASPEED_RESET_ADC] = 23, + [ASPEED_RESET_JTAG_MASTER] = 22, + [ASPEED_RESET_MIC] = 18, + [ASPEED_RESET_PWM] = 9, + [ASPEED_RESET_PCIVGA] = 8, + [ASPEED_RESET_I2C] = 2, + [ASPEED_RESET_AHB] = 1, +}; + +static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0); +} + +static int aspeed_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst); +} + +static int aspeed_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 val, rst = BIT(aspeed_resets[id]); + int ret; + + ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val); + if (ret) + return ret; + + return !!(val & rst); +} + +static const struct reset_control_ops aspeed_reset_ops = { + .assert = aspeed_reset_assert, + .deassert = aspeed_reset_deassert, + .status = aspeed_reset_status, +}; + static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, struct regmap *map, u8 clock_idx, u8 reset_idx, @@ -316,10 +379,11 @@ static int aspeed_clk_probe(struct platform_device *pdev) { const struct aspeed_clk_soc_data *soc_data; struct device *dev = &pdev->dev; + struct aspeed_reset *ar; struct regmap *map; struct clk_hw *hw; u32 val, rate; - int i; + int i, ret; map = syscon_node_to_regmap(dev->of_node); if (IS_ERR(map)) { @@ -327,6 +391,22 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(map); } + ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); + if (!ar) + return -ENOMEM; + + ar->map = map; + ar->rcdev.owner = THIS_MODULE; + ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets); + ar->rcdev.ops = &aspeed_reset_ops; + ar->rcdev.of_node = dev->of_node; + + ret = devm_reset_controller_register(dev, &ar->rcdev); + if (ret) { + dev_err(dev, "could not register reset controller\n"); + return ret; + } + /* SoC generations share common layouts but have different divisors */ soc_data = of_device_get_match_data(dev); if (!soc_data) { diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index 4a99421d77c8..8e19646d8025 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -39,4 +39,14 @@ #define ASPEED_NUM_CLKS 35 +#define ASPEED_RESET_XDMA 0 +#define ASPEED_RESET_MCTP 1 +#define ASPEED_RESET_ADC 2 +#define ASPEED_RESET_JTAG_MASTER 3 +#define ASPEED_RESET_MIC 4 +#define ASPEED_RESET_PWM 5 +#define ASPEED_RESET_PCIVGA 6 +#define ASPEED_RESET_I2C 7 +#define ASPEED_RESET_AHB 8 + #endif -- 2.14.1
WARNING: multiple messages have this Message-ID (diff)
From: joel@jms.id.au (Joel Stanley) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 5/5] clk: aspeed: Add reset controller Date: Mon, 30 Oct 2017 16:32:50 +1030 [thread overview] Message-ID: <20171030060250.701-6-joel@jms.id.au> (raw) In-Reply-To: <20171030060250.701-1-joel@jms.id.au> There are some resets that are not associated with gates. These are represented by a reset controller. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> --- v5: - Add Andrew's Reviewed-by v3: - Add named initalisers for the reset defines - Add define for ADC --- drivers/clk/clk-aspeed.c | 82 +++++++++++++++++++++++++++++++- include/dt-bindings/clock/aspeed-clock.h | 10 ++++ 2 files changed, 91 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index df5bc57a6ee2..d91e86c70e0c 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -17,6 +17,7 @@ #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> +#include <linux/reset-controller.h> #include <linux/slab.h> #include <linux/spinlock.h> @@ -275,6 +276,68 @@ static const struct clk_ops aspeed_clk_gate_ops = { .is_enabled = aspeed_clk_is_enabled, }; +/** + * struct aspeed_reset - Aspeed reset controller + * @map: regmap to access the containing system controller + * @rcdev: reset controller device + */ +struct aspeed_reset { + struct regmap *map; + struct reset_controller_dev rcdev; +}; + +#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) + +static const u8 aspeed_resets[] = { + [ASPEED_RESET_XDMA] = 25, + [ASPEED_RESET_MCTP] = 24, + [ASPEED_RESET_ADC] = 23, + [ASPEED_RESET_JTAG_MASTER] = 22, + [ASPEED_RESET_MIC] = 18, + [ASPEED_RESET_PWM] = 9, + [ASPEED_RESET_PCIVGA] = 8, + [ASPEED_RESET_I2C] = 2, + [ASPEED_RESET_AHB] = 1, +}; + +static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0); +} + +static int aspeed_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst); +} + +static int aspeed_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 val, rst = BIT(aspeed_resets[id]); + int ret; + + ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val); + if (ret) + return ret; + + return !!(val & rst); +} + +static const struct reset_control_ops aspeed_reset_ops = { + .assert = aspeed_reset_assert, + .deassert = aspeed_reset_deassert, + .status = aspeed_reset_status, +}; + static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, struct regmap *map, u8 clock_idx, u8 reset_idx, @@ -316,10 +379,11 @@ static int aspeed_clk_probe(struct platform_device *pdev) { const struct aspeed_clk_soc_data *soc_data; struct device *dev = &pdev->dev; + struct aspeed_reset *ar; struct regmap *map; struct clk_hw *hw; u32 val, rate; - int i; + int i, ret; map = syscon_node_to_regmap(dev->of_node); if (IS_ERR(map)) { @@ -327,6 +391,22 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(map); } + ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); + if (!ar) + return -ENOMEM; + + ar->map = map; + ar->rcdev.owner = THIS_MODULE; + ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets); + ar->rcdev.ops = &aspeed_reset_ops; + ar->rcdev.of_node = dev->of_node; + + ret = devm_reset_controller_register(dev, &ar->rcdev); + if (ret) { + dev_err(dev, "could not register reset controller\n"); + return ret; + } + /* SoC generations share common layouts but have different divisors */ soc_data = of_device_get_match_data(dev); if (!soc_data) { diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index 4a99421d77c8..8e19646d8025 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -39,4 +39,14 @@ #define ASPEED_NUM_CLKS 35 +#define ASPEED_RESET_XDMA 0 +#define ASPEED_RESET_MCTP 1 +#define ASPEED_RESET_ADC 2 +#define ASPEED_RESET_JTAG_MASTER 3 +#define ASPEED_RESET_MIC 4 +#define ASPEED_RESET_PWM 5 +#define ASPEED_RESET_PCIVGA 6 +#define ASPEED_RESET_I2C 7 +#define ASPEED_RESET_AHB 8 + #endif -- 2.14.1
next prev parent reply other threads:[~2017-10-30 6:04 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-10-30 6:02 [PATCH v5 0/5] clk: Add Aspeed clock driver Joel Stanley 2017-10-30 6:02 ` Joel Stanley 2017-10-30 6:02 ` [PATCH v5 1/5] clk: Add clock driver for ASPEED BMC SoCs Joel Stanley 2017-10-30 6:02 ` Joel Stanley 2017-10-30 6:02 ` [PATCH v5 2/5] clk: aspeed: Register core clocks Joel Stanley 2017-10-30 6:02 ` Joel Stanley 2017-11-13 5:03 ` Andrew Jeffery 2017-11-13 5:03 ` Andrew Jeffery 2017-10-30 6:02 ` [PATCH v5 3/5] clk: aspeed: Add platform driver and register PLLs Joel Stanley 2017-10-30 6:02 ` Joel Stanley 2017-11-13 5:04 ` Andrew Jeffery 2017-11-13 5:04 ` Andrew Jeffery 2017-10-30 6:02 ` [PATCH v5 4/5] clk: aspeed: Register gated clocks Joel Stanley 2017-10-30 6:02 ` Joel Stanley 2017-10-30 6:02 ` Joel Stanley [this message] 2017-10-30 6:02 ` [PATCH v5 5/5] clk: aspeed: Add reset controller Joel Stanley 2017-11-08 3:50 ` [PATCH v5 0/5] clk: Add Aspeed clock driver Joel Stanley 2017-11-08 3:50 ` Joel Stanley
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