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From: Yixun Lan <yixun.lan@amlogic.com>
To: Neil Armstrong <narmstrong@baylibre.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Kevin Hilman <khilman@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Carlo Caione <carlo@caione.org>,
	Yixun Lan <yixun.lan@amlogic.com>,
	Qiufang Dai <qiufang.dai@amlogic.com>,
	Jian Hu <jian.hu@amlogic.com>,
	<linux-amlogic@lists.infradead.org>, <devicetree@vger.kernel.org>,
	<linux-clk@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH v6 6/6] arm64: dts: meson-axg: switch uart_ao clock to CLK81
Date: Mon, 11 Dec 2017 14:48:53 +0800	[thread overview]
Message-ID: <20171211064853.32111-7-yixun.lan@amlogic.com> (raw)
In-Reply-To: <20171211064853.32111-1-yixun.lan@amlogic.com>

Switch the uart_ao pclk to CLK81 since the clock driver is ready.
Also move the clock info to the board.dts instead in the soc.dtsi.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi     | 5 +----
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..718bbebff107 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -19,4 +19,6 @@
 
 &uart_AO {
 	status = "okay";
+	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+	clock-names = "xtal", "pclk", "baud";
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 6fe5ee0c144e..f5b496bfd4de 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/axg-clkc.h>
 
 / {
 	compatible = "amlogic,meson-axg";
@@ -200,8 +201,6 @@
 				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
 				reg = <0x0 0x3000 0x0 0x18>;
 				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>, <&xtal>, <&xtal>;
-				clock-names = "xtal", "pclk", "baud";
 				status = "disabled";
 			};
 
@@ -209,8 +208,6 @@
 				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
 				reg = <0x0 0x4000 0x0 0x18>;
 				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>, <&xtal>, <&xtal>;
-				clock-names = "xtal", "pclk", "baud";
 				status = "disabled";
 			};
 		};
-- 
2.15.1

WARNING: multiple messages have this Message-ID (diff)
From: Yixun Lan <yixun.lan@amlogic.com>
To: Neil Armstrong <narmstrong@baylibre.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Kevin Hilman <khilman@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Carlo Caione <carlo@caione.org>,
	Yixun Lan <yixun.lan@amlogic.com>,
	Qiufang Dai <qiufang.dai@amlogic.com>,
	Jian Hu <jian.hu@amlogic.com>,
	linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v6 6/6] arm64: dts: meson-axg: switch uart_ao clock to CLK81
Date: Mon, 11 Dec 2017 14:48:53 +0800	[thread overview]
Message-ID: <20171211064853.32111-7-yixun.lan@amlogic.com> (raw)
In-Reply-To: <20171211064853.32111-1-yixun.lan@amlogic.com>

Switch the uart_ao pclk to CLK81 since the clock driver is ready.
Also move the clock info to the board.dts instead in the soc.dtsi.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi     | 5 +----
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..718bbebff107 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -19,4 +19,6 @@
 
 &uart_AO {
 	status = "okay";
+	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+	clock-names = "xtal", "pclk", "baud";
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 6fe5ee0c144e..f5b496bfd4de 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/axg-clkc.h>
 
 / {
 	compatible = "amlogic,meson-axg";
@@ -200,8 +201,6 @@
 				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
 				reg = <0x0 0x3000 0x0 0x18>;
 				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>, <&xtal>, <&xtal>;
-				clock-names = "xtal", "pclk", "baud";
 				status = "disabled";
 			};
 
@@ -209,8 +208,6 @@
 				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
 				reg = <0x0 0x4000 0x0 0x18>;
 				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>, <&xtal>, <&xtal>;
-				clock-names = "xtal", "pclk", "baud";
 				status = "disabled";
 			};
 		};
-- 
2.15.1

WARNING: multiple messages have this Message-ID (diff)
From: yixun.lan@amlogic.com (Yixun Lan)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 6/6] arm64: dts: meson-axg: switch uart_ao clock to CLK81
Date: Mon, 11 Dec 2017 14:48:53 +0800	[thread overview]
Message-ID: <20171211064853.32111-7-yixun.lan@amlogic.com> (raw)
In-Reply-To: <20171211064853.32111-1-yixun.lan@amlogic.com>

Switch the uart_ao pclk to CLK81 since the clock driver is ready.
Also move the clock info to the board.dts instead in the soc.dtsi.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi     | 5 +----
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..718bbebff107 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -19,4 +19,6 @@
 
 &uart_AO {
 	status = "okay";
+	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+	clock-names = "xtal", "pclk", "baud";
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 6fe5ee0c144e..f5b496bfd4de 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/axg-clkc.h>
 
 / {
 	compatible = "amlogic,meson-axg";
@@ -200,8 +201,6 @@
 				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
 				reg = <0x0 0x3000 0x0 0x18>;
 				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>, <&xtal>, <&xtal>;
-				clock-names = "xtal", "pclk", "baud";
 				status = "disabled";
 			};
 
@@ -209,8 +208,6 @@
 				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
 				reg = <0x0 0x4000 0x0 0x18>;
 				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>, <&xtal>, <&xtal>;
-				clock-names = "xtal", "pclk", "baud";
 				status = "disabled";
 			};
 		};
-- 
2.15.1

WARNING: multiple messages have this Message-ID (diff)
From: yixun.lan@amlogic.com (Yixun Lan)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH v6 6/6] arm64: dts: meson-axg: switch uart_ao clock to CLK81
Date: Mon, 11 Dec 2017 14:48:53 +0800	[thread overview]
Message-ID: <20171211064853.32111-7-yixun.lan@amlogic.com> (raw)
In-Reply-To: <20171211064853.32111-1-yixun.lan@amlogic.com>

Switch the uart_ao pclk to CLK81 since the clock driver is ready.
Also move the clock info to the board.dts instead in the soc.dtsi.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi     | 5 +----
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..718bbebff107 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -19,4 +19,6 @@
 
 &uart_AO {
 	status = "okay";
+	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+	clock-names = "xtal", "pclk", "baud";
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 6fe5ee0c144e..f5b496bfd4de 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/axg-clkc.h>
 
 / {
 	compatible = "amlogic,meson-axg";
@@ -200,8 +201,6 @@
 				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
 				reg = <0x0 0x3000 0x0 0x18>;
 				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>, <&xtal>, <&xtal>;
-				clock-names = "xtal", "pclk", "baud";
 				status = "disabled";
 			};
 
@@ -209,8 +208,6 @@
 				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
 				reg = <0x0 0x4000 0x0 0x18>;
 				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>, <&xtal>, <&xtal>;
-				clock-names = "xtal", "pclk", "baud";
 				status = "disabled";
 			};
 		};
-- 
2.15.1

  parent reply	other threads:[~2017-12-11  6:50 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-11  6:48 [PATCH v6 0/6] add clk controller driver for Meson-AXG SoC Yixun Lan
2017-12-11  6:48 ` Yixun Lan
2017-12-11  6:48 ` Yixun Lan
2017-12-11  6:48 ` Yixun Lan
2017-12-11  6:48 ` [PATCH v6 1/6] dt-bindings: clock: add compatible variant for the Meson-AXG Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  6:48 ` [PATCH v6 2/6] clk: meson-axg: add clocks dt-bindings required header Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  6:48 ` [PATCH v6 3/6] clk: meson-axg: add clock controller drivers Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  9:46   ` Jerome Brunet
2017-12-11  9:46     ` Jerome Brunet
2017-12-11  9:46     ` Jerome Brunet
2017-12-11  9:46     ` Jerome Brunet
2017-12-11 10:16     ` Yixun Lan
2017-12-11 10:16       ` Yixun Lan
2017-12-11 10:16       ` Yixun Lan
2017-12-11 10:16       ` Yixun Lan
2017-12-11 10:21       ` Jerome Brunet
2017-12-11 10:21         ` Jerome Brunet
2017-12-11 10:21         ` Jerome Brunet
2017-12-11 10:21         ` Jerome Brunet
2017-12-11  6:48 ` [PATCH v6 4/6] clk: meson: make the spinlock naming more specific Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  9:26   ` Jerome Brunet
2017-12-11  9:26     ` Jerome Brunet
2017-12-11  9:26     ` Jerome Brunet
2017-12-11  9:26     ` Jerome Brunet
2017-12-11  9:26     ` Jerome Brunet
2017-12-11 11:27   ` Jerome Brunet
2017-12-11 11:27     ` Jerome Brunet
2017-12-11 11:27     ` Jerome Brunet
2017-12-11 11:27     ` Jerome Brunet
2017-12-11  6:48 ` [PATCH v6 5/6] arm64: dts: meson-axg: add clock DT info for Meson AXG SoC Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  6:48 ` Yixun Lan [this message]
2017-12-11  6:48   ` [PATCH v6 6/6] arm64: dts: meson-axg: switch uart_ao clock to CLK81 Yixun Lan
2017-12-11  6:48   ` Yixun Lan
2017-12-11  6:48   ` Yixun Lan

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