All of lore.kernel.org
 help / color / mirror / Atom feed
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>, <linux-omap@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <nsekhar@ti.com>, <kishon@ti.com>
Subject: [PATCH v2 2/3] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7
Date: Tue, 19 Dec 2017 14:28:22 +0530	[thread overview]
Message-ID: <20171219085823.8695-3-kishon@ti.com> (raw)
In-Reply-To: <20171219085823.8695-1-kishon@ti.com>

Add syscon properties required for configuring PCIe in x2 lane mode.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 Documentation/devicetree/bindings/pci/ti-pci.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 82cb875e4cec..bfbc77ac7355 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -13,6 +13,12 @@ PCIe DesignWare Controller
  - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
 	       where <X> is the instance number of the pcie from the HW spec.
  - num-lanes as specified in ../designware-pcie.txt
+ - ti,syscon-lane-conf : phandle/offset pair. Phandle to the system control
+			 module and the register offset to specify 1 lane or
+			 2 lane.
+ - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
+			module and the register offset to specify lane
+			selection.
 
 HOST MODE
 =========
-- 
2.11.0

WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	linux-omap@vger.kernel.org, devicetree@vger.kernel.org,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	nsekhar@ti.com, kishon@ti.com
Subject: [PATCH v2 2/3] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7
Date: Tue, 19 Dec 2017 14:28:22 +0530	[thread overview]
Message-ID: <20171219085823.8695-3-kishon@ti.com> (raw)
In-Reply-To: <20171219085823.8695-1-kishon@ti.com>

Add syscon properties required for configuring PCIe in x2 lane mode.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 Documentation/devicetree/bindings/pci/ti-pci.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 82cb875e4cec..bfbc77ac7355 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -13,6 +13,12 @@ PCIe DesignWare Controller
  - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
 	       where <X> is the instance number of the pcie from the HW spec.
  - num-lanes as specified in ../designware-pcie.txt
+ - ti,syscon-lane-conf : phandle/offset pair. Phandle to the system control
+			 module and the register offset to specify 1 lane or
+			 2 lane.
+ - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
+			module and the register offset to specify lane
+			selection.
 
 HOST MODE
 =========
-- 
2.11.0

  parent reply	other threads:[~2017-12-19  8:58 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-19  8:58 [PATCH v2 0/3] PCI: dra7xx: Support PCIe x2 lane mode Kishon Vijay Abraham I
2017-12-19  8:58 ` Kishon Vijay Abraham I
2017-12-19  8:58 ` [PATCH v2 1/3] dt-bindings: PCI: dra7xx: Add SoC specific compatible strings Kishon Vijay Abraham I
2017-12-19  8:58   ` Kishon Vijay Abraham I
2017-12-19  8:58 ` Kishon Vijay Abraham I [this message]
2017-12-19  8:58   ` [PATCH v2 2/3] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7 Kishon Vijay Abraham I
2017-12-20 18:57   ` Rob Herring
2017-12-20 18:57     ` Rob Herring
2017-12-22  6:03     ` Kishon Vijay Abraham I
2017-12-22  6:03       ` Kishon Vijay Abraham I
2017-12-22 18:24       ` Tony Lindgren
2017-12-26 17:46         ` Rob Herring
2017-12-26 17:46           ` Rob Herring
2017-12-26 18:10           ` Tony Lindgren
2017-12-26 18:10             ` Tony Lindgren
2017-12-26 18:10             ` Tony Lindgren
2017-12-27  6:40             ` Kishon Vijay Abraham I
2017-12-27  6:40               ` Kishon Vijay Abraham I
2017-12-27  6:40               ` Kishon Vijay Abraham I
2017-12-19  8:58 ` [PATCH v2 3/3] PCI: dra7xx: Enable x2 mode support for dra74x, dra76x and dra72x Kishon Vijay Abraham I
2017-12-19  8:58   ` Kishon Vijay Abraham I
2018-02-26 10:30   ` Lorenzo Pieralisi
2018-02-28 12:04     ` Kishon Vijay Abraham I
2018-02-28 12:04       ` Kishon Vijay Abraham I

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20171219085823.8695-3-kishon@ti.com \
    --to=kishon@ti.com \
    --cc=bhelgaas@google.com \
    --cc=devicetree@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-omap@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=mark.rutland@arm.com \
    --cc=nsekhar@ti.com \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.