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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Tony Lindgren <tony@atomide.com>, <bcousson@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Russell King <linux@armlinux.org.uk>, <linux-pci@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-omap@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <nsekhar@ti.com>,
	<kishon@ti.com>
Subject: [PATCH 1/7] ARM: dts: dra7: Add properties to enable PCIe x2 lane mode
Date: Tue, 19 Dec 2017 15:01:27 +0530	[thread overview]
Message-ID: <20171219093133.16565-2-kishon@ti.com> (raw)
In-Reply-To: <20171219093133.16565-1-kishon@ti.com>

ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable
PCIe x2 lane mode are added here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index ac9216293b7c..9966d82dbd7c 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -309,6 +309,8 @@
 				ti,hwmods = "pcie1";
 				phys = <&pcie1_phy>;
 				phy-names = "pcie-phy0";
+				ti,syscon-lane-conf = <&scm_conf 0x558>;
+				ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
 				interrupt-map-mask = <0 0 0 7>;
 				interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 						<0 0 0 2 &pcie1_intc 2>,
@@ -334,6 +336,8 @@
 				phys = <&pcie1_phy>;
 				phy-names = "pcie-phy0";
 				ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
+				ti,syscon-lane-conf = <&scm_conf 0x558>;
+				ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
 				status = "disabled";
 			};
 		};
-- 
2.11.0

WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
To: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>,
	bcousson-rdvid1DuHRBWk0Htik3J/w@public.gmane.org
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>,
	linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	nsekhar-l0cyMroinI0@public.gmane.org,
	kishon-l0cyMroinI0@public.gmane.org
Subject: [PATCH 1/7] ARM: dts: dra7: Add properties to enable PCIe x2 lane mode
Date: Tue, 19 Dec 2017 15:01:27 +0530	[thread overview]
Message-ID: <20171219093133.16565-2-kishon@ti.com> (raw)
In-Reply-To: <20171219093133.16565-1-kishon-l0cyMroinI0@public.gmane.org>

ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable
PCIe x2 lane mode are added here.

Signed-off-by: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
Signed-off-by: Sekhar Nori <nsekhar-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/dra7.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index ac9216293b7c..9966d82dbd7c 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -309,6 +309,8 @@
 				ti,hwmods = "pcie1";
 				phys = <&pcie1_phy>;
 				phy-names = "pcie-phy0";
+				ti,syscon-lane-conf = <&scm_conf 0x558>;
+				ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
 				interrupt-map-mask = <0 0 0 7>;
 				interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 						<0 0 0 2 &pcie1_intc 2>,
@@ -334,6 +336,8 @@
 				phys = <&pcie1_phy>;
 				phy-names = "pcie-phy0";
 				ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
+				ti,syscon-lane-conf = <&scm_conf 0x558>;
+				ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
 				status = "disabled";
 			};
 		};
-- 
2.11.0

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WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Tony Lindgren <tony@atomide.com>, <bcousson@baylibre.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org, kishon@ti.com,
	linux-pci@vger.kernel.org, nsekhar@ti.com,
	Russell King <linux@armlinux.org.uk>,
	linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/7] ARM: dts: dra7: Add properties to enable PCIe x2 lane mode
Date: Tue, 19 Dec 2017 15:01:27 +0530	[thread overview]
Message-ID: <20171219093133.16565-2-kishon@ti.com> (raw)
In-Reply-To: <20171219093133.16565-1-kishon@ti.com>

ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable
PCIe x2 lane mode are added here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index ac9216293b7c..9966d82dbd7c 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -309,6 +309,8 @@
 				ti,hwmods = "pcie1";
 				phys = <&pcie1_phy>;
 				phy-names = "pcie-phy0";
+				ti,syscon-lane-conf = <&scm_conf 0x558>;
+				ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
 				interrupt-map-mask = <0 0 0 7>;
 				interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 						<0 0 0 2 &pcie1_intc 2>,
@@ -334,6 +336,8 @@
 				phys = <&pcie1_phy>;
 				phy-names = "pcie-phy0";
 				ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
+				ti,syscon-lane-conf = <&scm_conf 0x558>;
+				ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
 				status = "disabled";
 			};
 		};
-- 
2.11.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: kishon@ti.com (Kishon Vijay Abraham I)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/7] ARM: dts: dra7: Add properties to enable PCIe x2 lane mode
Date: Tue, 19 Dec 2017 15:01:27 +0530	[thread overview]
Message-ID: <20171219093133.16565-2-kishon@ti.com> (raw)
In-Reply-To: <20171219093133.16565-1-kishon@ti.com>

ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable
PCIe x2 lane mode are added here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index ac9216293b7c..9966d82dbd7c 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -309,6 +309,8 @@
 				ti,hwmods = "pcie1";
 				phys = <&pcie1_phy>;
 				phy-names = "pcie-phy0";
+				ti,syscon-lane-conf = <&scm_conf 0x558>;
+				ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
 				interrupt-map-mask = <0 0 0 7>;
 				interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 						<0 0 0 2 &pcie1_intc 2>,
@@ -334,6 +336,8 @@
 				phys = <&pcie1_phy>;
 				phy-names = "pcie-phy0";
 				ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
+				ti,syscon-lane-conf = <&scm_conf 0x558>;
+				ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
 				status = "disabled";
 			};
 		};
-- 
2.11.0

  reply	other threads:[~2017-12-19  9:32 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-19  9:31 [PATCH 0/7] ARM: dts: dra7: Enable x2 lane mode support Kishon Vijay Abraham I
2017-12-19  9:31 ` Kishon Vijay Abraham I
2017-12-19  9:31 ` Kishon Vijay Abraham I
2017-12-19  9:31 ` Kishon Vijay Abraham I
2017-12-19  9:31 ` Kishon Vijay Abraham I [this message]
2017-12-19  9:31   ` [PATCH 1/7] ARM: dts: dra7: Add properties to enable PCIe x2 lane mode Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31 ` [PATCH 2/7] ARM: dts: DRA74x: Use PCIe compatible specific to dra74 Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31 ` [PATCH 3/7] ARM: dts: DRA72x: Use PCIe compatible specific to dra72 Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31 ` [PATCH 4/7] ARM: dts: dra76-evm: Enable x2 PCIe lanes Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31 ` [PATCH 5/7] ARM: dts: dra7: Remove deprecated PCI compatible string Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31 ` [PATCH 6/7] ARM: omap2plus_defconfig: Enable CONFIG_PCI_DRA7XX (Host & Device modes) Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31 ` [PATCH 7/7] ARM: multi_v7_defconfig: " Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-19  9:31   ` Kishon Vijay Abraham I
2017-12-21 15:13 ` [PATCH 0/7] ARM: dts: dra7: Enable x2 lane mode support Tony Lindgren
2017-12-21 15:13   ` Tony Lindgren
2017-12-21 15:13   ` Tony Lindgren
2018-03-07 12:08 ` Lorenzo Pieralisi
2018-03-07 12:08   ` Lorenzo Pieralisi
2018-03-07 12:08   ` Lorenzo Pieralisi
2018-03-07 12:27   ` Kishon Vijay Abraham I
2018-03-07 12:27     ` Kishon Vijay Abraham I
2018-03-07 12:27     ` Kishon Vijay Abraham I
2018-03-07 12:27     ` Kishon Vijay Abraham I

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