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From: luc.michel@greensocs.com
To: qemu-devel@nongnu.org
Cc: Luc MICHEL <luc.michel@git.antfield.fr>,
	qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
	"Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
	Alistair Francis <alistair.francis@xilinx.com>
Subject: [Qemu-devel] [PATCH 1/4] hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and pending"
Date: Fri, 19 Jan 2018 15:57:53 +0100	[thread overview]
Message-ID: <20180119145756.7629-3-luc.michel@greensocs.com> (raw)
In-Reply-To: <20180119145756.7629-1-luc.michel@greensocs.com>

From: Luc MICHEL <luc.michel@git.antfield.fr>

In the GIC, when an IRQ is acknowledged, its state goes from "pending"
to:
   - "active" if the corresponding IRQ pin has been de-asserted
   - "active and pending" otherwise.
The GICv2 manual states that when a IRQ becomes active (or active and
pending), the GIC should either signal another (higher priority) IRQ to
the CPU if there is one, or de-assert the CPU IRQ pin.

The current implementation of the GIC in QEMU does not check if the
IRQ is already active when looking for pending interrupts with
sufficient priority in gic_update(). This can lead to signaling an
interrupt that is already active.

This usually happens when splitting priority drop and interrupt
deactivation. On priority drop, the IRQ stays active until deactivation.
If it becomes pending again, chances are that it will be incorrectly
selected as best_irq in gic_update().

This commit fixes this by checking if the IRQ is not already active when
looking for best_irq in gic_update().

Note that regarding the ARM11MPCore GIC version, the corresponding
manual is not clear on that point, but it has has no priority
drop/interrupt deactivation separation, so this case should not happen.

Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr>
---
 hw/intc/arm_gic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index d701e49ff9..dad383ea12 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -93,6 +93,7 @@ void gic_update(GICState *s)
         best_irq = 1023;
         for (irq = 0; irq < s->num_irq; irq++) {
             if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) &&
+                (!GIC_TEST_ACTIVE(irq, cm)) &&
                 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) {
                 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
                     best_prio = GIC_GET_PRIORITY(irq, cpu);
-- 
2.16.0

  reply	other threads:[~2018-01-19 14:58 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-19 14:57 [Qemu-devel] [PATCH 0/4] arm_gic: Various fixes luc.michel
2018-01-19 14:57 ` luc.michel [this message]
2018-01-19 14:57 ` [Qemu-devel] [PATCH 2/4] hw/intc/arm_gic: Fix C_RPR value on idle priority luc.michel
2018-01-19 14:57 ` [Qemu-devel] [PATCH 3/4] hw/intc/arm_gic: Fix group priority computation for group 1 IRQs luc.michel
2018-01-22 15:25   ` Peter Maydell
2018-01-19 14:57 ` [Qemu-devel] [PATCH 4/4] hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1 luc.michel
2018-01-22 15:19   ` Peter Maydell
2018-01-22 15:25     ` Luc Michel
2018-01-22 15:36 ` [Qemu-devel] [PATCH 0/4] arm_gic: Various fixes Peter Maydell

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