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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH 04/10] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
Date: Mon, 29 Jan 2018 15:22:17 -0800	[thread overview]
Message-ID: <20180129232223.766-4-rodrigo.vivi@intel.com> (raw)
In-Reply-To: <20180129232223.766-1-rodrigo.vivi@intel.com>

This was wrong since its introduction on commit '04416108ccea
("drm/i915/cnl: Add registers related to voltage swing sequences.")'

But since no Port F was needed so far we don't need to
propagate fixes back there.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dda77443cb89..31e2fa602620 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1964,7 +1964,7 @@ enum i915_power_well_id {
 #define _CNL_PORT_TX_DW2_LN0_B		0x162648
 #define _CNL_PORT_TX_DW2_LN0_C		0x162C48
 #define _CNL_PORT_TX_DW2_LN0_D		0x162E48
-#define _CNL_PORT_TX_DW2_LN0_F		0x162A48
+#define _CNL_PORT_TX_DW2_LN0_F		0x162848
 #define CNL_PORT_TX_DW2_GRP(port)	_MMIO_PORT6(port, \
 						    _CNL_PORT_TX_DW2_GRP_AE, \
 						    _CNL_PORT_TX_DW2_GRP_B, \
-- 
2.13.6

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  parent reply	other threads:[~2018-01-29 23:22 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-29 23:22 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
2018-01-29 23:22 ` [PATCH 02/10] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
2018-01-29 23:22 ` [PATCH 03/10] drm/i915/cnl: Extend Wa 1178 to Aux F Rodrigo Vivi
2018-01-29 23:22 ` Rodrigo Vivi [this message]
2018-01-29 23:22 ` [PATCH 05/10] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F Rodrigo Vivi
2018-01-29 23:22 ` [PATCH 06/10] drm/i915/cnl: Add right GMBUS pin number for HDMI on " Rodrigo Vivi
2018-01-29 23:22 ` [PATCH 07/10] drm/i915: For HPD connected port use hpd_pin instead of port Rodrigo Vivi
2018-01-29 23:22 ` [PATCH 08/10] drm/i915/cnl: Add HPD support for Port F Rodrigo Vivi
2018-01-29 23:22 ` [PATCH 09/10] drm/i915/cnl: Enable DDI-F on Cannonlake Rodrigo Vivi
2018-01-29 23:22 ` [PATCH 10/10] drm/i915/cnl: Fix DP max rate for Cannonlake with port F Rodrigo Vivi
2018-01-30  7:45   ` Jani Nikula
2018-01-30 20:42     ` Rodrigo Vivi
2018-01-30 20:46       ` Ville Syrjälä
2018-01-31  0:51         ` Rodrigo Vivi
2018-01-29 23:45 ` ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Patchwork
2018-01-30  2:44 ` ✗ Fi.CI.IGT: warning " Patchwork
2018-01-30 20:05 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-01-30 20:37   ` Rodrigo Vivi
  -- strict thread matches above, loose matches on Subject: below --
2018-01-25 22:03 [PATCH 01/10] " Rodrigo Vivi
2018-01-25 22:03 ` [PATCH 04/10] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition Rodrigo Vivi
2018-01-25 19:27 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
2018-01-25 19:27 ` [PATCH 04/10] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition Rodrigo Vivi

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