From: Andrzej Hajda <a.hajda@samsung.com> To: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Andrzej Hajda <a.hajda@samsung.com>, Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>, Marek Szyprowski <m.szyprowski@samsung.com>, Tomasz Figa <tomasz.figa@gmail.com>, Chanwoo Choi <cw00.choi@samsung.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Kukjin Kim <kgene@kernel.org>, Krzysztof Kozlowski <krzk@kernel.org>, linux-samsung-soc@vger.kernel.org (moderated list:SAMSUNG SOC CLOCK DRIVERS), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK) Subject: [PATCH v2 2/7] clk: samsung: exynos5250: fix PLL rates Date: Fri, 16 Feb 2018 15:57:49 +0100 [thread overview] Message-ID: <20180216145754.14428-3-a.hajda@samsung.com> (raw) In-Reply-To: <20180216145754.14428-1-a.hajda@samsung.com> Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. If that is not the case, rate of parent might be being set not as expected. For instance, if in the PLL rates table we have a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate will return 393216003. If we now attempt to set rate of a PLL's child divider clock to 393216000/2 its rate will be 131072001, rather than 196608000. That is the divider will be set to 3 instead of 2, because 393216003/2 is greater than 196608000. To fix this issue declared rates are changed to exactly match rates generated by a PLL, as calculated from the P, M, S, K coefficients. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> --- drivers/clk/samsung/clk-exynos5250.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 9b073c98a891..923c608b1b95 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -711,13 +711,13 @@ static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ PLL_36XX_RATE(192000000, 64, 2, 2, 0), - PLL_36XX_RATE(180633600, 90, 3, 2, 20762), + PLL_36XX_RATE(180633605, 90, 3, 2, 20762), PLL_36XX_RATE(180000000, 90, 3, 2, 0), PLL_36XX_RATE(73728000, 98, 2, 4, 19923), - PLL_36XX_RATE(67737600, 90, 2, 4, 20762), + PLL_36XX_RATE(67737602, 90, 2, 4, 20762), PLL_36XX_RATE(49152000, 98, 3, 4, 19923), - PLL_36XX_RATE(45158400, 90, 3, 4, 20762), - PLL_36XX_RATE(32768000, 131, 3, 5, 4719), + PLL_36XX_RATE(45158401, 90, 3, 4, 20762), + PLL_36XX_RATE(32768001, 131, 3, 5, 4719), { }, }; -- 2.16.1
WARNING: multiple messages have this Message-ID (diff)
From: Andrzej Hajda <a.hajda@samsung.com> To: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Andrzej Hajda <a.hajda@samsung.com>, Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>, Marek Szyprowski <m.szyprowski@samsung.com>, Tomasz Figa <tomasz.figa@gmail.com>, Chanwoo Choi <cw00.choi@samsung.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Kukjin Kim <kgene@kernel.org>, Krzysztof Kozlowski <krzk@kernel.org>, "moderated list:SAMSUNG SOC CLOCK DRIVERS" <linux-samsung-soc@vger.kernel.org>, "open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org> Subject: [PATCH v2 2/7] clk: samsung: exynos5250: fix PLL rates Date: Fri, 16 Feb 2018 15:57:49 +0100 [thread overview] Message-ID: <20180216145754.14428-3-a.hajda@samsung.com> (raw) In-Reply-To: <20180216145754.14428-1-a.hajda@samsung.com> Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. If that is not the case, rate of parent might be being set not as expected. For instance, if in the PLL rates table we have a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate will return 393216003. If we now attempt to set rate of a PLL's child divider clock to 393216000/2 its rate will be 131072001, rather than 196608000. That is the divider will be set to 3 instead of 2, because 393216003/2 is greater than 196608000. To fix this issue declared rates are changed to exactly match rates generated by a PLL, as calculated from the P, M, S, K coefficients. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> --- drivers/clk/samsung/clk-exynos5250.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 9b073c98a891..923c608b1b95 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -711,13 +711,13 @@ static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ PLL_36XX_RATE(192000000, 64, 2, 2, 0), - PLL_36XX_RATE(180633600, 90, 3, 2, 20762), + PLL_36XX_RATE(180633605, 90, 3, 2, 20762), PLL_36XX_RATE(180000000, 90, 3, 2, 0), PLL_36XX_RATE(73728000, 98, 2, 4, 19923), - PLL_36XX_RATE(67737600, 90, 2, 4, 20762), + PLL_36XX_RATE(67737602, 90, 2, 4, 20762), PLL_36XX_RATE(49152000, 98, 3, 4, 19923), - PLL_36XX_RATE(45158400, 90, 3, 4, 20762), - PLL_36XX_RATE(32768000, 131, 3, 5, 4719), + PLL_36XX_RATE(45158401, 90, 3, 4, 20762), + PLL_36XX_RATE(32768001, 131, 3, 5, 4719), { }, }; -- 2.16.1
next prev parent reply other threads:[~2018-02-16 14:57 UTC|newest] Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CGME20180216145803eucas1p2b75e6f26d2979ee129152f674a31e886@eucas1p2.samsung.com> 2018-02-16 14:57 ` [PATCH v2 0/7] clk: samsung: fix PLL rates Andrzej Hajda 2018-02-16 14:57 ` Andrzej Hajda [not found] ` <CGME20180216145804eucas1p2cbe4de00131e6b7bbd946d349dfc2b2d@eucas1p2.samsung.com> 2018-02-16 14:57 ` [PATCH v2 1/7] clk: samsung: exynos3250: " Andrzej Hajda 2018-02-16 14:57 ` Andrzej Hajda [not found] ` <CGME20180216145804eucas1p20cc58695fce84f9acc03a16b6913fcb2@eucas1p2.samsung.com> 2018-02-16 14:57 ` Andrzej Hajda [this message] 2018-02-16 14:57 ` [PATCH v2 2/7] clk: samsung: exynos5250: " Andrzej Hajda [not found] ` <CGME20180216145805eucas1p14670777cd5339fda26b95c71b726f866@eucas1p1.samsung.com> 2018-02-16 14:57 ` [PATCH v2 3/7] clk: samsung: exynos5260: " Andrzej Hajda 2018-02-16 14:57 ` Andrzej Hajda 2018-02-19 6:27 ` Chanwoo Choi [not found] ` <CGME20180216145805eucas1p28452227465bf275bb00dec65ab5b3978@eucas1p2.samsung.com> 2018-02-16 14:57 ` [PATCH v2 4/7] clk: samsung: exynos5433: " Andrzej Hajda 2018-02-16 14:57 ` Andrzej Hajda 2018-02-19 6:27 ` Chanwoo Choi [not found] ` <CGME20180216145806eucas1p1e939d3138e29d3446df90e1a69ea9624@eucas1p1.samsung.com> 2018-02-16 14:57 ` [PATCH v2 5/7] clk: samsung: exynos7: " Andrzej Hajda 2018-02-16 14:57 ` Andrzej Hajda 2018-02-19 6:28 ` Chanwoo Choi [not found] ` <CGME20180216145807eucas1p2260082a8178bc746dc8110982f2b0c2b@eucas1p2.samsung.com> 2018-02-16 14:57 ` [PATCH v2 6/7] clk: samsung: s3c2410: " Andrzej Hajda 2018-02-16 14:57 ` Andrzej Hajda 2018-02-20 7:10 ` Chanwoo Choi [not found] ` <CGME20180216145807eucas1p27282e8889ea210ee082a5ffa3c94a4ff@eucas1p2.samsung.com> 2018-02-16 14:57 ` [PATCH v2 7/7] clk: samsung: add compile time PLL rate validators Andrzej Hajda 2018-02-16 14:57 ` Andrzej Hajda 2018-02-19 9:44 ` Chanwoo Choi 2018-02-19 10:07 ` Andrzej Hajda [not found] ` <CGME20180220070544eucas1p17987a47caeba1c07a1d82eb852fcd3b1@eucas1p1.samsung.com> 2018-02-20 7:05 ` [PATCH v3 " Andrzej Hajda 2018-02-20 7:10 ` Chanwoo Choi 2018-03-06 16:46 ` [PATCH v2 0/7] clk: samsung: fix PLL rates Sylwester Nawrocki
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