From: Marc Zyngier <marc.zyngier@arm.com> To: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, Kristina Martsenko <kristina.martsenko@arm.com> Subject: [PATCH v6 13/26] arm64; insn: Add encoder for the EXTR instruction Date: Wed, 14 Mar 2018 16:50:36 +0000 [thread overview] Message-ID: <20180314165049.30105-14-marc.zyngier@arm.com> (raw) In-Reply-To: <20180314165049.30105-1-marc.zyngier@arm.com> Add an encoder for the EXTR instruction, which also implements the ROR variant (where Rn == Rm). Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm64/include/asm/insn.h | 6 ++++++ arch/arm64/kernel/insn.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index 815b35bc53ed..f62c56b1793f 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -319,6 +319,7 @@ __AARCH64_INSN_FUNCS(and_imm, 0x7F800000, 0x12000000) __AARCH64_INSN_FUNCS(orr_imm, 0x7F800000, 0x32000000) __AARCH64_INSN_FUNCS(eor_imm, 0x7F800000, 0x52000000) __AARCH64_INSN_FUNCS(ands_imm, 0x7F800000, 0x72000000) +__AARCH64_INSN_FUNCS(extr, 0x7FA00000, 0x13800000) __AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000) __AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000) __AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000) @@ -433,6 +434,11 @@ u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type, enum aarch64_insn_register Rn, enum aarch64_insn_register Rd, u64 imm); +u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant, + enum aarch64_insn_register Rm, + enum aarch64_insn_register Rn, + enum aarch64_insn_register Rd, + u8 lsb); u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base, enum aarch64_insn_prfm_type type, enum aarch64_insn_prfm_target target, diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index e87d6dcd7c82..2929adaad587 100644 --- a/arch/arm64/kernel/insn.c +++ b/arch/arm64/kernel/insn.c @@ -1621,3 +1621,35 @@ u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type, insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn); return aarch64_encode_immediate(imm, variant, insn); } + +u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant, + enum aarch64_insn_register Rm, + enum aarch64_insn_register Rn, + enum aarch64_insn_register Rd, + u8 lsb) +{ + u32 insn; + + insn = aarch64_insn_get_extr_value(); + + switch (variant) { + case AARCH64_INSN_VARIANT_32BIT: + if (lsb > 31) + return AARCH64_BREAK_FAULT; + break; + case AARCH64_INSN_VARIANT_64BIT: + if (lsb > 63) + return AARCH64_BREAK_FAULT; + insn |= AARCH64_INSN_SF_BIT; + insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_N, insn, 1); + break; + default: + pr_err("%s: unknown variant encoding %d\n", __func__, variant); + return AARCH64_BREAK_FAULT; + } + + insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, lsb); + insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd); + insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn); + return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, Rm); +} -- 2.14.2
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 13/26] arm64; insn: Add encoder for the EXTR instruction Date: Wed, 14 Mar 2018 16:50:36 +0000 [thread overview] Message-ID: <20180314165049.30105-14-marc.zyngier@arm.com> (raw) In-Reply-To: <20180314165049.30105-1-marc.zyngier@arm.com> Add an encoder for the EXTR instruction, which also implements the ROR variant (where Rn == Rm). Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm64/include/asm/insn.h | 6 ++++++ arch/arm64/kernel/insn.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index 815b35bc53ed..f62c56b1793f 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -319,6 +319,7 @@ __AARCH64_INSN_FUNCS(and_imm, 0x7F800000, 0x12000000) __AARCH64_INSN_FUNCS(orr_imm, 0x7F800000, 0x32000000) __AARCH64_INSN_FUNCS(eor_imm, 0x7F800000, 0x52000000) __AARCH64_INSN_FUNCS(ands_imm, 0x7F800000, 0x72000000) +__AARCH64_INSN_FUNCS(extr, 0x7FA00000, 0x13800000) __AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000) __AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000) __AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000) @@ -433,6 +434,11 @@ u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type, enum aarch64_insn_register Rn, enum aarch64_insn_register Rd, u64 imm); +u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant, + enum aarch64_insn_register Rm, + enum aarch64_insn_register Rn, + enum aarch64_insn_register Rd, + u8 lsb); u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base, enum aarch64_insn_prfm_type type, enum aarch64_insn_prfm_target target, diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index e87d6dcd7c82..2929adaad587 100644 --- a/arch/arm64/kernel/insn.c +++ b/arch/arm64/kernel/insn.c @@ -1621,3 +1621,35 @@ u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type, insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn); return aarch64_encode_immediate(imm, variant, insn); } + +u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant, + enum aarch64_insn_register Rm, + enum aarch64_insn_register Rn, + enum aarch64_insn_register Rd, + u8 lsb) +{ + u32 insn; + + insn = aarch64_insn_get_extr_value(); + + switch (variant) { + case AARCH64_INSN_VARIANT_32BIT: + if (lsb > 31) + return AARCH64_BREAK_FAULT; + break; + case AARCH64_INSN_VARIANT_64BIT: + if (lsb > 63) + return AARCH64_BREAK_FAULT; + insn |= AARCH64_INSN_SF_BIT; + insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_N, insn, 1); + break; + default: + pr_err("%s: unknown variant encoding %d\n", __func__, variant); + return AARCH64_BREAK_FAULT; + } + + insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, lsb); + insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd); + insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn); + return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, Rm); +} -- 2.14.2
next prev parent reply other threads:[~2018-03-14 16:50 UTC|newest] Thread overview: 124+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-03-14 16:50 [PATCH v6 00/26] KVM/arm64: Randomise EL2 mappings (variant 3a mitigation) Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 01/26] arm64: alternatives: Add dynamic patching feature Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 02/26] arm64: insn: Add N immediate encoding Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 03/26] arm64: insn: Add encoder for bitwise operations using literals Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 04/26] arm64: KVM: Dynamically patch the kernel/hyp VA mask Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-15 19:15 ` James Morse 2018-03-15 19:15 ` James Morse 2018-03-16 8:52 ` Marc Zyngier 2018-03-16 8:52 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 05/26] arm64: cpufeatures: Drop the ARM64_HYP_OFFSET_LOW feature flag Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 06/26] KVM: arm/arm64: Do not use kern_hyp_va() with kvm_vgic_global_state Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-15 19:16 ` James Morse 2018-03-15 19:16 ` James Morse 2018-03-16 9:31 ` Marc Zyngier 2018-03-16 9:31 ` Marc Zyngier 2018-03-16 11:35 ` Andrew Jones 2018-03-16 11:35 ` Andrew Jones 2018-03-16 11:38 ` Ard Biesheuvel 2018-03-16 11:38 ` Ard Biesheuvel 2018-03-16 11:51 ` Marc Zyngier 2018-03-16 11:51 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 07/26] KVM: arm/arm64: Demote HYP VA range display to being a debug feature Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 08/26] KVM: arm/arm64: Move ioremap calls to create_hyp_io_mappings Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 09/26] KVM: arm/arm64: Keep GICv2 HYP VAs in kvm_vgic_global_state Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 10/26] KVM: arm/arm64: Fix idmap size and alignment Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-15 19:15 ` James Morse 2018-03-15 19:15 ` James Morse 2018-03-16 8:55 ` Marc Zyngier 2018-03-16 8:55 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 11/26] KVM: arm64: Fix HYP idmap unmap when using 52bit PA Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-16 16:07 ` Catalin Marinas 2018-03-16 16:07 ` Catalin Marinas 2018-03-16 16:47 ` Suzuki K Poulose 2018-03-16 16:47 ` Suzuki K Poulose 2018-03-14 16:50 ` [PATCH v6 12/26] KVM: arm/arm64: Move HYP IO VAs to the "idmap" range Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-15 19:09 ` James Morse 2018-03-15 19:09 ` James Morse 2018-03-16 8:44 ` Marc Zyngier 2018-03-16 8:44 ` Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier [this message] 2018-03-14 16:50 ` [PATCH v6 13/26] arm64; insn: Add encoder for the EXTR instruction Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 14/26] arm64: insn: Allow ADD/SUB (immediate) with LSL #12 Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 15/26] arm64: KVM: Dynamically compute the HYP VA mask Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 16/26] arm64: KVM: Introduce EL2 VA randomisation Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 17/26] arm64: Update the KVM memory map documentation Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 18/26] arm64: KVM: Move vector offsetting from hyp-init.S to kvm_get_hyp_vector Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 19/26] arm64: KVM: Move stashing of x0/x1 into the vector code itself Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-15 14:39 ` Andrew Jones 2018-03-15 14:39 ` Andrew Jones 2018-03-16 16:22 ` Catalin Marinas 2018-03-16 16:22 ` Catalin Marinas 2018-03-16 16:37 ` Marc Zyngier 2018-03-16 16:37 ` Marc Zyngier 2018-03-16 16:38 ` Marc Zyngier 2018-03-16 16:38 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 20/26] arm64: KVM: Move BP hardening vectors into .hyp.text section Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-15 14:42 ` Andrew Jones 2018-03-15 14:42 ` Andrew Jones 2018-03-16 16:24 ` Catalin Marinas 2018-03-16 16:24 ` Catalin Marinas 2018-03-14 16:50 ` [PATCH v6 21/26] arm64: KVM: Reserve 4 additional instructions in the BPI template Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-15 14:46 ` Andrew Jones 2018-03-15 14:46 ` Andrew Jones 2018-03-16 16:30 ` Catalin Marinas 2018-03-16 16:30 ` Catalin Marinas 2018-03-14 16:50 ` [PATCH v6 22/26] arm64: KVM: Allow far branches from vector slots to the main vectors Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 23/26] arm/arm64: KVM: Introduce EL2-specific executable mappings Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-15 15:03 ` Andrew Jones 2018-03-15 15:03 ` Andrew Jones 2018-03-15 15:53 ` Marc Zyngier 2018-03-15 15:53 ` Marc Zyngier 2018-03-14 16:50 ` [PATCH v6 24/26] arm64: Make BP hardening slot counter available Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-15 15:05 ` Andrew Jones 2018-03-15 15:05 ` Andrew Jones 2018-03-14 16:50 ` [PATCH v6 25/26] arm64: KVM: Allow mapping of vectors outside of the RAM region Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-15 15:54 ` Andrew Jones 2018-03-15 15:54 ` Andrew Jones 2018-03-15 16:17 ` Marc Zyngier 2018-03-15 16:17 ` Marc Zyngier 2018-03-15 17:08 ` Andrew Jones 2018-03-15 17:08 ` Andrew Jones 2018-03-15 18:47 ` Marc Zyngier 2018-03-15 18:47 ` Marc Zyngier 2018-03-16 12:33 ` Andrew Jones 2018-03-16 12:33 ` Andrew Jones 2018-03-14 16:50 ` [PATCH v6 26/26] arm64: Enable ARM64_HARDEN_EL2_VECTORS on Cortex-A57 and A72 Marc Zyngier 2018-03-14 16:50 ` Marc Zyngier 2018-03-15 15:57 ` [PATCH v6 00/26] KVM/arm64: Randomise EL2 mappings (variant 3a mitigation) Andrew Jones 2018-03-15 15:57 ` Andrew Jones 2018-03-15 16:19 ` Marc Zyngier 2018-03-15 16:19 ` Marc Zyngier 2018-03-15 16:40 ` Andrew Jones 2018-03-15 16:40 ` Andrew Jones 2018-03-15 16:52 ` Marc Zyngier 2018-03-15 16:52 ` Marc Zyngier 2018-03-16 17:46 ` Catalin Marinas 2018-03-16 17:46 ` Catalin Marinas 2018-03-16 18:05 ` Marc Zyngier 2018-03-16 18:05 ` Marc Zyngier
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