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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 3/8] drm/i915/icl: Update subslice define for ICL 11
Date: Fri, 16 Mar 2018 14:14:51 +0200	[thread overview]
Message-ID: <20180316121456.11577-3-mika.kuoppala@linux.intel.com> (raw)
In-Reply-To: <20180316121456.11577-1-mika.kuoppala@linux.intel.com>

From: Kelvin Gardiner <kelvin.gardiner@intel.com>

ICL 11 has a greater number of maximum subslices. This patch
reflects this.

v2: GEN11 updates to MCR_SELECTOR (Oscar)
v3: Copypasta error in the new defines (Lionel)

Bspec: 21139
BSpec: 21108

Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com> (v1)
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> (v1)
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         |  4 ++++
 drivers/gpu/drm/i915/intel_engine_cs.c  | 22 ++++++++++++++++++----
 drivers/gpu/drm/i915/intel_ringbuffer.h |  2 +-
 3 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 982e72e73e99..e29ff9dd967e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2151,6 +2151,10 @@ enum i915_power_well_id {
 #define   GEN8_MCR_SLICE_MASK		GEN8_MCR_SLICE(3)
 #define   GEN8_MCR_SUBSLICE(subslice)	(((subslice) & 3) << 24)
 #define   GEN8_MCR_SUBSLICE_MASK	GEN8_MCR_SUBSLICE(3)
+#define   GEN11_MCR_SLICE(slice)	(((slice) & 0xf) << 27)
+#define   GEN11_MCR_SLICE_MASK		GEN11_MCR_SLICE(0xf)
+#define   GEN11_MCR_SUBSLICE(subslice)	(((subslice) & 0x7) << 24)
+#define   GEN11_MCR_SUBSLICE_MASK	GEN11_MCR_SUBSLICE(0x7)
 #define RING_IPEIR(base)	_MMIO((base)+0x64)
 #define RING_IPEHR(base)	_MMIO((base)+0x68)
 /*
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 337dfa56a738..de09fa42a509 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -800,10 +800,24 @@ static inline uint32_t
 read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 		  int subslice, i915_reg_t reg)
 {
+	uint32_t mcr_slice_subslice_mask;
+	uint32_t mcr_slice_subslice_select;
 	uint32_t mcr;
 	uint32_t ret;
 	enum forcewake_domains fw_domains;
 
+	if (INTEL_GEN(dev_priv) >= 11) {
+		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
+					  GEN11_MCR_SUBSLICE_MASK;
+		mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
+					    GEN11_MCR_SUBSLICE(subslice);
+	} else {
+		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
+					  GEN8_MCR_SUBSLICE_MASK;
+		mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
+					    GEN8_MCR_SUBSLICE(subslice);
+	}
+
 	fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
 						    FW_REG_READ);
 	fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
@@ -818,14 +832,14 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	 * The HW expects the slice and sublice selectors to be reset to 0
 	 * after reading out the registers.
 	 */
-	WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
-	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
-	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+	mcr &= ~mcr_slice_subslice_mask;
+	mcr |= mcr_slice_subslice_select;
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	ret = I915_READ_FW(reg);
 
-	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+	mcr &= ~mcr_slice_subslice_mask;
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 1f50727a5ddb..a02c7b3b9d55 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -86,7 +86,7 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
 }
 
 #define I915_MAX_SLICES	3
-#define I915_MAX_SUBSLICES 3
+#define I915_MAX_SUBSLICES 8
 
 #define instdone_slice_mask(dev_priv__) \
 	(INTEL_GEN(dev_priv__) == 7 ? \
-- 
2.14.1

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  parent reply	other threads:[~2018-03-16 12:15 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-16 12:14 [PATCH 1/8] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances Mika Kuoppala
2018-03-16 12:14 ` [PATCH 2/8] drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11 Mika Kuoppala
2018-03-16 12:14 ` Mika Kuoppala [this message]
2018-03-20 14:34   ` [PATCH 3/8] drm/i915/icl: Update subslice define for ICL 11 Mika Kuoppala
2018-03-16 12:14 ` [PATCH 4/8] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection Mika Kuoppala
2018-03-16 12:18   ` Lionel Landwerlin
2018-03-16 13:06   ` [PATCH v2 " Lionel Landwerlin
2018-03-16 12:14 ` [PATCH 5/8] drm/i915/icl: Add reset control register changes Mika Kuoppala
2018-03-16 12:22   ` Mika Kuoppala
2018-03-16 12:45   ` Chris Wilson
2018-03-16 20:28   ` Daniele Ceraolo Spurio
2018-03-16 21:55     ` Chris Wilson
2018-03-27 16:26     ` Michel Thierry
2018-03-16 12:14 ` [PATCH 6/8] drm/i915/icl: Handle RPS interrupts correctly for Gen11 Mika Kuoppala
2018-03-16 12:14 ` [PATCH 7/8] drm/i915/icl: Enable RC6 and RPS in Gen11 Mika Kuoppala
2018-03-16 12:14 ` [PATCH 8/8] drm/i915/icl: Use hw engine class, instance to find irq handler Mika Kuoppala
2018-03-16 18:28   ` Michel Thierry
2018-03-16 19:37     ` Daniele Ceraolo Spurio
2018-03-19 15:14       ` Daniele Ceraolo Spurio
2018-03-16 13:53 ` ✓ Fi.CI.BAT: success for series starting with [1/8] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances (rev2) Patchwork
2018-03-16 17:01 ` ✓ Fi.CI.IGT: " Patchwork
2018-03-19 15:26 ` [PATCH 1/8] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances Sagar Arun Kamble
2018-10-18  9:47   ` Tvrtko Ursulin
2018-03-23 16:28 ` Lionel Landwerlin
2018-03-27 22:42   ` Paulo Zanoni
2018-03-27 23:39     ` Paulo Zanoni
2018-03-28 11:36       ` Lionel Landwerlin

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