From: Miquel Raynal <miquel.raynal@bootlin.com> To: Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <marc.zyngier@arm.com> Cc: Mark Rutland <mark.rutland@arm.com>, Andrew Lunn <andrew@lunn.ch>, devicetree@vger.kernel.org, Antoine Tenart <antoine.tenart@bootlin.com>, Catalin Marinas <catalin.marinas@arm.com>, Gregory Clement <gregory.clement@bootlin.com>, Haim Boot <hayim@marvell.com>, Will Deacon <will.deacon@arm.com>, Maxime Chevallier <maxime.chevallier@bootlin.com>, Nadav Haklai <nadavh@marvell.com>, Rob Herring <robh+dt@kernel.org>, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Miquel Raynal <miquel.raynal@bootlin.com>, Hanna Hawa <hannah@marvell.com>, linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Subject: [PATCH 13/17] dt-bindings/interrupt-controller: update Marvell ICU bindings Date: Sat, 21 Apr 2018 15:55:33 +0200 [thread overview] Message-ID: <20180421135537.24716-14-miquel.raynal@bootlin.com> (raw) In-Reply-To: <20180421135537.24716-1-miquel.raynal@bootlin.com> Change the documentation to reflect the new bindings used for Marvell ICU. This involves describing each interrupt group as a subnode of the ICU node. Each of them having their own compatible. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- .../bindings/interrupt-controller/marvell,icu.txt | 60 ++++++++++++++++------ 1 file changed, 43 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt index 649b7ec9d9b1..b856e91105e4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt @@ -5,6 +5,8 @@ The Marvell ICU (Interrupt Consolidation Unit) controller is responsible for collecting all wired-interrupt sources in the CP and communicating them to the GIC in the AP, the unit translates interrupt requests on input wires to MSG memory mapped transactions to the GIC. +These messages will access a different GIC memory area depending on +their type (NSR, SR, SEI, REI, etc). Required properties: @@ -12,20 +14,19 @@ Required properties: - reg: Should contain ICU registers location and length. +Subnodes: Each group of interrupt is declared as a subnode of the ICU, +with their own compatible. + +Required properties for the icu_nsr/icu_sei subnodes: + +- compatible: Should be "marvell,cp110-icu-nsr" or "marvell,cp110-icu-sei". + - #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value shall be 3. + interrupt source. The value shall be 2. - The 1st cell is the group type of the ICU interrupt. Possible group - types are: + The 1st cell is the index of the interrupt in the ICU unit. - ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure - ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure - ICU_GRP_SEI (0x4) : System error interrupt - ICU_GRP_REI (0x5) : RAM error interrupt - - The 2nd cell is the index of the interrupt in the ICU unit. - - The 3rd cell is the type of the interrupt. See arm,gic.txt for + The 2nd cell is the type of the interrupt. See arm,gic.txt for details. - interrupt-controller: Identifies the node as an interrupt @@ -35,17 +36,42 @@ Required properties: that allows to trigger interrupts using MSG memory mapped transactions. +Note: each 'interrupts' property referring to any 'icu_xxx' node shall + have a different number within [0:206]. + Example: icu: interrupt-controller@1e0000 { compatible = "marvell,cp110-icu"; reg = <0x1e0000 0x440>; - #interrupt-cells = <3>; - interrupt-controller; - msi-parent = <&gicp>; + + CP110_LABEL(icu_nsr): icu-nsr { + compatible = "marvell,cp110-icu-nsr"; + #interrupt-cells = <2>; + interrupt-controller; + msi-parent = <&gicp>; + }; + + CP110_LABEL(icu_sei): icu-sei { + compatible = "marvell,cp110-icu-sei"; + #interrupt-cells = <2>; + interrupt-controller; + msi-parent = <&sei>; + }; +}; + +node1 { + interrupt-parent = <&icu_nsr>; + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; +}; + +node2 { + interrupt-parent = <&icu_sei>; + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; }; -usb3h0: usb3@500000 { - interrupt-parent = <&icu>; - interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; +/* Would not work with the above nodes */ +node3 { + interrupt-parent = <&icu_nsr>; + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; }; -- 2.14.1
WARNING: multiple messages have this Message-ID (diff)
From: miquel.raynal@bootlin.com (Miquel Raynal) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 13/17] dt-bindings/interrupt-controller: update Marvell ICU bindings Date: Sat, 21 Apr 2018 15:55:33 +0200 [thread overview] Message-ID: <20180421135537.24716-14-miquel.raynal@bootlin.com> (raw) In-Reply-To: <20180421135537.24716-1-miquel.raynal@bootlin.com> Change the documentation to reflect the new bindings used for Marvell ICU. This involves describing each interrupt group as a subnode of the ICU node. Each of them having their own compatible. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- .../bindings/interrupt-controller/marvell,icu.txt | 60 ++++++++++++++++------ 1 file changed, 43 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt index 649b7ec9d9b1..b856e91105e4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt @@ -5,6 +5,8 @@ The Marvell ICU (Interrupt Consolidation Unit) controller is responsible for collecting all wired-interrupt sources in the CP and communicating them to the GIC in the AP, the unit translates interrupt requests on input wires to MSG memory mapped transactions to the GIC. +These messages will access a different GIC memory area depending on +their type (NSR, SR, SEI, REI, etc). Required properties: @@ -12,20 +14,19 @@ Required properties: - reg: Should contain ICU registers location and length. +Subnodes: Each group of interrupt is declared as a subnode of the ICU, +with their own compatible. + +Required properties for the icu_nsr/icu_sei subnodes: + +- compatible: Should be "marvell,cp110-icu-nsr" or "marvell,cp110-icu-sei". + - #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value shall be 3. + interrupt source. The value shall be 2. - The 1st cell is the group type of the ICU interrupt. Possible group - types are: + The 1st cell is the index of the interrupt in the ICU unit. - ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure - ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure - ICU_GRP_SEI (0x4) : System error interrupt - ICU_GRP_REI (0x5) : RAM error interrupt - - The 2nd cell is the index of the interrupt in the ICU unit. - - The 3rd cell is the type of the interrupt. See arm,gic.txt for + The 2nd cell is the type of the interrupt. See arm,gic.txt for details. - interrupt-controller: Identifies the node as an interrupt @@ -35,17 +36,42 @@ Required properties: that allows to trigger interrupts using MSG memory mapped transactions. +Note: each 'interrupts' property referring to any 'icu_xxx' node shall + have a different number within [0:206]. + Example: icu: interrupt-controller at 1e0000 { compatible = "marvell,cp110-icu"; reg = <0x1e0000 0x440>; - #interrupt-cells = <3>; - interrupt-controller; - msi-parent = <&gicp>; + + CP110_LABEL(icu_nsr): icu-nsr { + compatible = "marvell,cp110-icu-nsr"; + #interrupt-cells = <2>; + interrupt-controller; + msi-parent = <&gicp>; + }; + + CP110_LABEL(icu_sei): icu-sei { + compatible = "marvell,cp110-icu-sei"; + #interrupt-cells = <2>; + interrupt-controller; + msi-parent = <&sei>; + }; +}; + +node1 { + interrupt-parent = <&icu_nsr>; + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; +}; + +node2 { + interrupt-parent = <&icu_sei>; + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; }; -usb3h0: usb3 at 500000 { - interrupt-parent = <&icu>; - interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; +/* Would not work with the above nodes */ +node3 { + interrupt-parent = <&icu_nsr>; + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; }; -- 2.14.1
next prev parent reply other threads:[~2018-04-21 13:55 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-04-21 13:55 [PATCH 00/17] Add System Error Interrupt support to Armada SoCs Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-04-21 13:55 ` [PATCH 01/17] dt-bindings/interrupt-controller: fix Marvell ICU length in the example Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-04-27 20:16 ` Rob Herring 2018-04-27 20:16 ` Rob Herring 2018-04-30 13:44 ` Thomas Petazzoni 2018-04-30 13:44 ` Thomas Petazzoni 2018-04-21 13:55 ` [PATCH 02/17] arm64: dts: marvell: fix CP110 ICU node size Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-04-30 12:38 ` Gregory CLEMENT 2018-04-30 12:38 ` Gregory CLEMENT 2018-04-30 13:44 ` Thomas Petazzoni 2018-04-30 13:44 ` Thomas Petazzoni 2018-04-21 13:55 ` [PATCH 03/17] arm64: dts: marvell: add syscon compatible to CP110 ICU node Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-04-30 13:45 ` Thomas Petazzoni 2018-04-30 13:45 ` Thomas Petazzoni 2018-04-21 13:55 ` [PATCH 04/17] irqchip/irq-mvebu-icu: fix wrong user data retrieval Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-04-30 13:49 ` Thomas Petazzoni 2018-04-30 13:49 ` Thomas Petazzoni 2018-05-03 14:57 ` Miquel Raynal 2018-05-03 14:57 ` Miquel Raynal 2018-04-21 13:55 ` [PATCH 05/17] irqchip/irq-mvebu-icu: clarify the reset operation of configured interrupts Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-04-30 13:51 ` Thomas Petazzoni 2018-04-30 13:51 ` Thomas Petazzoni 2018-04-21 13:55 ` [PATCH 06/17] irqchip/irq-mvebu-icu: switch to regmap Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-04-30 12:42 ` Gregory CLEMENT 2018-04-30 12:42 ` Gregory CLEMENT 2018-04-30 13:53 ` Thomas Petazzoni 2018-04-30 13:53 ` Thomas Petazzoni 2018-05-03 15:05 ` Miquel Raynal 2018-05-03 15:05 ` Miquel Raynal 2018-04-30 13:58 ` Thomas Petazzoni 2018-04-30 13:58 ` Thomas Petazzoni 2018-04-21 13:55 ` [PATCH 07/17] irqchip/irq-mvebu-icu: make irq_domain local Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-05-02 8:02 ` Thomas Petazzoni 2018-05-02 8:02 ` Thomas Petazzoni 2018-04-21 13:55 ` [PATCH 08/17] irqchip/irq-mvebu-icu: disociate ICU and NSR Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-05-02 8:03 ` Thomas Petazzoni 2018-05-02 8:03 ` Thomas Petazzoni 2018-04-21 13:55 ` [PATCH 09/17] irqchip/irq-mvebu-icu: support ICU subnodes Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-05-02 8:13 ` Thomas Petazzoni 2018-05-02 8:13 ` Thomas Petazzoni 2018-05-04 8:32 ` Miquel Raynal 2018-05-04 8:32 ` Miquel Raynal 2018-04-21 13:55 ` [PATCH 10/17] irqchip/irq-mvebu-sei: add new driver for Marvell SEI Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-05-02 9:17 ` Thomas Petazzoni 2018-05-02 9:17 ` Thomas Petazzoni 2018-05-02 15:56 ` Thomas Petazzoni 2018-05-02 15:56 ` Thomas Petazzoni 2018-05-18 13:22 ` Miquel Raynal 2018-05-18 13:22 ` Miquel Raynal 2018-04-21 13:55 ` [PATCH 11/17] arm64: marvell: enable SEI driver Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-04-30 13:01 ` Gregory CLEMENT 2018-04-30 13:01 ` Gregory CLEMENT 2018-04-21 13:55 ` [PATCH 12/17] irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI) Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal [this message] 2018-04-21 13:55 ` [PATCH 13/17] dt-bindings/interrupt-controller: update Marvell ICU bindings Miquel Raynal 2018-04-27 20:47 ` Rob Herring 2018-04-27 20:47 ` Rob Herring 2018-04-28 10:42 ` Miquel Raynal 2018-04-28 10:42 ` Miquel Raynal 2018-04-28 10:50 ` Thomas Petazzoni 2018-04-28 10:50 ` Thomas Petazzoni 2018-04-21 13:55 ` [PATCH 14/17] dt-bindings/interrupt-controller: add description for Marvell SEI node Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-04-27 20:50 ` Rob Herring 2018-04-27 20:50 ` Rob Herring 2018-04-28 10:48 ` Miquel Raynal 2018-04-28 10:48 ` Miquel Raynal 2018-04-30 14:09 ` Rob Herring 2018-04-30 14:09 ` Rob Herring 2018-05-18 14:48 ` Miquel Raynal 2018-05-18 14:48 ` Miquel Raynal 2018-04-30 14:24 ` Thomas Petazzoni 2018-04-30 14:24 ` Thomas Petazzoni 2018-04-21 13:55 ` [PATCH 15/17] arm64: dts: marvell: add AP806 SEI subnode Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-04-21 13:55 ` [PATCH 16/17] arm64: dts: marvell: use new bindings for CP110 interrupts Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal 2018-04-21 13:55 ` [PATCH 17/17] arm64: dts: marvell: add CP110 ICU SEI subnode Miquel Raynal 2018-04-21 13:55 ` Miquel Raynal
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