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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, sai.pavan.boddu@xilinx.com,
	alistair@alistair23.me, frasse.iglesias@gmail.com,
	edgar.iglesias@xilinx.com
Subject: [Qemu-devel] [PULL v1 2/5] target-microblaze: Fix trap checks for FPU insns
Date: Mon, 30 Apr 2018 17:08:34 +0200	[thread overview]
Message-ID: <20180430150837.20470-3-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <20180430150837.20470-1-edgar.iglesias@gmail.com>

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Fix trap checks for FPU insns when extended FPU insns are enabled.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index f739751930..ec12fed49d 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1412,7 +1412,7 @@ static void dec_fpu(DisasContext *dc)
 
     if ((dc->tb_flags & MSR_EE_FLAG)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
-          && (dc->cpu->cfg.use_fpu != 1)) {
+          && !dc->cpu->cfg.use_fpu) {
         tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
         t_gen_raise_exception(dc, EXCP_HW_EXCP);
         return;
-- 
2.14.1

  parent reply	other threads:[~2018-04-30 15:08 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-30 15:08 [Qemu-devel] [PULL v1 0/5] Xilinx queue 2018-04-30 Edgar E. Iglesias
2018-04-30 15:08 ` [Qemu-devel] [PULL v1 1/5] target-microblaze: Respect MSR.PVR as read-only Edgar E. Iglesias
2018-04-30 15:08 ` Edgar E. Iglesias [this message]
2018-04-30 15:08 ` [Qemu-devel] [PULL v1 3/5] target-microblaze: Don't clobber the IMM reg for ld/st reversed Edgar E. Iglesias
2018-04-30 15:08 ` [Qemu-devel] [PULL v1 4/5] target-microblaze: mmu: Make TLBSX write-only Edgar E. Iglesias
2018-04-30 15:08 ` [Qemu-devel] [PULL v1 5/5] target-microblaze: mmu: Make the TLBX MISS bit read-only Edgar E. Iglesias
2018-04-30 16:16 ` [Qemu-devel] [PULL v1 0/5] Xilinx queue 2018-04-30 Peter Maydell

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