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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, sai.pavan.boddu@xilinx.com,
	alistair@alistair23.me, frasse.iglesias@gmail.com,
	edgar.iglesias@xilinx.com
Subject: [Qemu-devel] [PULL v1 4/5] target-microblaze: mmu: Make TLBSX write-only
Date: Mon, 30 Apr 2018 17:08:36 +0200	[thread overview]
Message-ID: <20180430150837.20470-5-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <20180430150837.20470-1-edgar.iglesias@gmail.com>

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Make TLBSX write-only and guest-error log reads from it.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/mmu.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index a0f06758f8..8391811900 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -182,7 +182,7 @@ done:
 uint32_t mmu_read(CPUMBState *env, uint32_t rn)
 {
     unsigned int i;
-    uint32_t r;
+    uint32_t r = 0;
 
     if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
         qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
@@ -211,6 +211,9 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
             }
             r = env->mmu.regs[rn];
             break;
+        case MMU_R_TLBSX:
+            qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n");
+            break;
         default:
             r = env->mmu.regs[rn];
             break;
-- 
2.14.1

  parent reply	other threads:[~2018-04-30 15:08 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-30 15:08 [Qemu-devel] [PULL v1 0/5] Xilinx queue 2018-04-30 Edgar E. Iglesias
2018-04-30 15:08 ` [Qemu-devel] [PULL v1 1/5] target-microblaze: Respect MSR.PVR as read-only Edgar E. Iglesias
2018-04-30 15:08 ` [Qemu-devel] [PULL v1 2/5] target-microblaze: Fix trap checks for FPU insns Edgar E. Iglesias
2018-04-30 15:08 ` [Qemu-devel] [PULL v1 3/5] target-microblaze: Don't clobber the IMM reg for ld/st reversed Edgar E. Iglesias
2018-04-30 15:08 ` Edgar E. Iglesias [this message]
2018-04-30 15:08 ` [Qemu-devel] [PULL v1 5/5] target-microblaze: mmu: Make the TLBX MISS bit read-only Edgar E. Iglesias
2018-04-30 16:16 ` [Qemu-devel] [PULL v1 0/5] Xilinx queue 2018-04-30 Peter Maydell

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