From: "Marty E. Plummer" <hanetzer-zVALfsKDk1AS+FvcfC7Uqw@public.gmane.org> To: u-boot-0aAXYlwwYIKGBzrmiIFOJg@public.gmane.org Cc: vagrant-8fiUuRrzOP0dnm+yROfE0A@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, "Marty E. Plummer" <hanetzer-zVALfsKDk1AS+FvcfC7Uqw@public.gmane.org> Subject: [PATCH 3/3] rockchip: fix incorrect detection of ram size Date: Sun, 6 May 2018 09:25:13 -0500 [thread overview] Message-ID: <20180506142513.19911-4-hanetzer@startmail.com> (raw) In-Reply-To: <20180506142513.19911-1-hanetzer-zVALfsKDk1AS+FvcfC7Uqw@public.gmane.org> Taken from coreboot's src/soc/rockchip/rk3288/sdram.c Without this change, my u-boot build for the asus c201 chromebook (4GiB) is incorrectly detected as 0 Bytes of ram. Signed-off-by: Marty E. Plummer <hanetzer-zVALfsKDk1AS+FvcfC7Uqw@public.gmane.org> --- arch/arm/mach-rockchip/sdram_common.c | 62 ++++++++++++++++----------- 1 file changed, 37 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c index 76dbdc8715..a9c9f970a4 100644 --- a/arch/arm/mach-rockchip/sdram_common.c +++ b/arch/arm/mach-rockchip/sdram_common.c @@ -10,6 +10,8 @@ #include <asm/io.h> #include <asm/arch/sdram_common.h> #include <dm/uclass-internal.h> +#include <linux/kernel.h> +#include <linux/sizes.h> DECLARE_GLOBAL_DATA_PTR; size_t rockchip_sdram_size(phys_addr_t reg) @@ -19,34 +21,44 @@ size_t rockchip_sdram_size(phys_addr_t reg) size_t size_mb = 0; u32 ch; - u32 sys_reg = readl(reg); - u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) - & SYS_REG_NUM_CH_MASK); + if (!size_mb) { - debug("%s %x %x\n", __func__, (u32)reg, sys_reg); - for (ch = 0; ch < ch_num; ch++) { - rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & - SYS_REG_RANK_MASK); - col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); - bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); - cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & - SYS_REG_CS0_ROW_MASK); - cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & - SYS_REG_CS1_ROW_MASK); - bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & - SYS_REG_BW_MASK)); - row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & - SYS_REG_ROW_3_4_MASK; + u32 sys_reg = readl(reg); + u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) + & SYS_REG_NUM_CH_MASK); - chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); + debug("%s %x %x\n", __func__, (u32)reg, sys_reg); + for (ch = 0; ch < ch_num; ch++) { + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & + SYS_REG_RANK_MASK); + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & + SYS_REG_CS0_ROW_MASK); + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & + SYS_REG_CS1_ROW_MASK); + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & + SYS_REG_BW_MASK)); + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & + SYS_REG_ROW_3_4_MASK; - if (rank > 1) - chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); - if (row_3_4) - chipsize_mb = chipsize_mb * 3 / 4; - size_mb += chipsize_mb; - debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n", - rank, col, bk, cs0_row, bw, row_3_4); + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); + + if (rank > 1) + chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); + if (row_3_4) + chipsize_mb = chipsize_mb * 3 / 4; + size_mb += chipsize_mb; + debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n", + rank, col, bk, cs0_row, bw, row_3_4); + } + + /* + * we use the 0x00000000~0xfeffffff space + * since 0xff000000~0xffffffff is soc register space + * so we reserve it + */ + size_mb = min(size_mb, 0xff000000/SZ_1M); } return (size_t)size_mb << 20; -- 2.17.0
WARNING: multiple messages have this Message-ID (diff)
From: Marty E. Plummer <hanetzer@startmail.com> To: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 3/3] rockchip: fix incorrect detection of ram size Date: Sun, 6 May 2018 09:25:13 -0500 [thread overview] Message-ID: <20180506142513.19911-4-hanetzer@startmail.com> (raw) In-Reply-To: <20180506142513.19911-1-hanetzer@startmail.com> Taken from coreboot's src/soc/rockchip/rk3288/sdram.c Without this change, my u-boot build for the asus c201 chromebook (4GiB) is incorrectly detected as 0 Bytes of ram. Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> --- arch/arm/mach-rockchip/sdram_common.c | 62 ++++++++++++++++----------- 1 file changed, 37 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c index 76dbdc8715..a9c9f970a4 100644 --- a/arch/arm/mach-rockchip/sdram_common.c +++ b/arch/arm/mach-rockchip/sdram_common.c @@ -10,6 +10,8 @@ #include <asm/io.h> #include <asm/arch/sdram_common.h> #include <dm/uclass-internal.h> +#include <linux/kernel.h> +#include <linux/sizes.h> DECLARE_GLOBAL_DATA_PTR; size_t rockchip_sdram_size(phys_addr_t reg) @@ -19,34 +21,44 @@ size_t rockchip_sdram_size(phys_addr_t reg) size_t size_mb = 0; u32 ch; - u32 sys_reg = readl(reg); - u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) - & SYS_REG_NUM_CH_MASK); + if (!size_mb) { - debug("%s %x %x\n", __func__, (u32)reg, sys_reg); - for (ch = 0; ch < ch_num; ch++) { - rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & - SYS_REG_RANK_MASK); - col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); - bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); - cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & - SYS_REG_CS0_ROW_MASK); - cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & - SYS_REG_CS1_ROW_MASK); - bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & - SYS_REG_BW_MASK)); - row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & - SYS_REG_ROW_3_4_MASK; + u32 sys_reg = readl(reg); + u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) + & SYS_REG_NUM_CH_MASK); - chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); + debug("%s %x %x\n", __func__, (u32)reg, sys_reg); + for (ch = 0; ch < ch_num; ch++) { + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & + SYS_REG_RANK_MASK); + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & + SYS_REG_CS0_ROW_MASK); + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & + SYS_REG_CS1_ROW_MASK); + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & + SYS_REG_BW_MASK)); + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & + SYS_REG_ROW_3_4_MASK; - if (rank > 1) - chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); - if (row_3_4) - chipsize_mb = chipsize_mb * 3 / 4; - size_mb += chipsize_mb; - debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n", - rank, col, bk, cs0_row, bw, row_3_4); + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); + + if (rank > 1) + chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); + if (row_3_4) + chipsize_mb = chipsize_mb * 3 / 4; + size_mb += chipsize_mb; + debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n", + rank, col, bk, cs0_row, bw, row_3_4); + } + + /* + * we use the 0x00000000~0xfeffffff space + * since 0xff000000~0xffffffff is soc register space + * so we reserve it + */ + size_mb = min(size_mb, 0xff000000/SZ_1M); } return (size_t)size_mb << 20; -- 2.17.0
next prev parent reply other threads:[~2018-05-06 14:25 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-05-06 14:25 [PATCH 0/3] add support for the asus C201 chromebook (4GiB) Marty E. Plummer 2018-05-06 14:25 ` [U-Boot] " Marty E. Plummer [not found] ` <20180506142513.19911-1-hanetzer-zVALfsKDk1AS+FvcfC7Uqw@public.gmane.org> 2018-05-06 14:25 ` [PATCH 1/3] sf: Add GigaDevice gd25q32b entry Marty E. Plummer 2018-05-06 14:25 ` [U-Boot] " Marty E. Plummer 2018-05-09 8:57 ` [U-Boot,1/3] " Philipp Tomsich 2018-05-09 8:57 ` [U-Boot] " Philipp Tomsich 2018-05-06 14:25 ` [PATCH 2/3] rockchip: add support for veyron-speedy (ASUS Chromebook C201) Marty E. Plummer 2018-05-06 14:25 ` [U-Boot] " Marty E. Plummer 2018-05-06 22:12 ` klaus.goger at theobroma-systems.com 2018-05-07 0:20 ` Marty E. Plummer 2018-07-13 10:31 ` Dr. Philipp Tomsich 2018-07-24 5:12 ` Marty E. Plummer 2018-07-24 8:05 ` Dr. Philipp Tomsich 2018-05-06 14:25 ` Marty E. Plummer [this message] 2018-05-06 14:25 ` [U-Boot] [PATCH 3/3] rockchip: fix incorrect detection of ram size Marty E. Plummer 2018-05-06 18:39 ` klaus.goger at theobroma-systems.com 2018-05-06 19:08 ` Marty E. Plummer 2018-05-06 20:03 ` Marty E. Plummer 2018-05-06 20:21 ` klaus.goger at theobroma-systems.com 2018-05-06 20:41 ` Marty E. Plummer 2018-05-06 22:19 ` Dr. Philipp Tomsich 2018-05-06 22:19 ` [U-Boot] " Dr. Philipp Tomsich 2018-05-07 0:25 ` Marty E. Plummer 2018-05-07 0:25 ` [U-Boot] " Marty E. Plummer 2018-05-07 2:20 ` Kever Yang 2018-05-07 2:20 ` [U-Boot] " Kever Yang 2018-05-07 2:34 ` Marty E. Plummer 2018-05-07 2:34 ` [U-Boot] " Marty E. Plummer 2018-05-07 9:16 ` Dr. Philipp Tomsich 2018-05-07 9:16 ` [U-Boot] " Dr. Philipp Tomsich [not found] ` <791299C0-EEC0-4DB1-97C4-A8DAD3B1A481-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org> 2018-05-08 0:52 ` Marty E. Plummer 2018-05-08 0:52 ` Marty E. Plummer 2018-05-08 10:21 ` Dr. Philipp Tomsich 2018-05-08 10:21 ` [U-Boot] " Dr. Philipp Tomsich 2018-05-08 10:23 ` Dr. Philipp Tomsich 2018-05-08 10:23 ` [U-Boot] " Dr. Philipp Tomsich 2018-05-08 19:21 ` Marty E. Plummer 2018-05-08 19:21 ` [U-Boot] " Marty E. Plummer 2018-05-08 21:08 ` Dr. Philipp Tomsich 2018-05-08 21:08 ` [U-Boot] " Dr. Philipp Tomsich [not found] ` <C5B7DFAE-C5CA-4D9E-B6CB-C44E9AD974E9-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org> 2018-05-09 5:29 ` Marty E. Plummer 2018-05-09 5:29 ` Marty E. Plummer 2018-05-09 7:24 ` Dr. Philipp Tomsich 2018-05-09 7:24 ` [U-Boot] " Dr. Philipp Tomsich 2018-05-14 15:56 ` Dr. Philipp Tomsich 2018-05-14 15:56 ` [U-Boot] " Dr. Philipp Tomsich 2018-05-19 10:40 ` Marty E. Plummer 2018-05-19 12:08 ` Dr. Philipp Tomsich 2018-07-06 3:11 ` Marty E. Plummer 2018-07-24 8:07 ` Dr. Philipp Tomsich 2018-07-25 16:28 ` Carlo Caione 2018-07-10 14:41 ` Simon Glass 2018-07-10 14:41 ` [U-Boot] " Simon Glass 2018-07-10 18:55 ` Dr. Philipp Tomsich 2018-07-10 18:55 ` [U-Boot] " Dr. Philipp Tomsich 2018-05-07 0:32 ` [U-Boot] [PATCH 0/3] add support for the asus C201 chromebook (4GiB) Marty E. Plummer
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