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From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v5 3/7] drm/i915/perf: simplify configure all context function
Date: Mon, 14 May 2018 16:55:56 +0100	[thread overview]
Message-ID: <20180514155600.16521-4-lionel.g.landwerlin@intel.com> (raw)
In-Reply-To: <20180514155600.16521-1-lionel.g.landwerlin@intel.com>

We don't need any special treatment on error so just return as soon as
possible.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 019bd2d073ad..94466aeafd02 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1765,7 +1765,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
 	/* Switch away from any user context. */
 	ret = gen8_switch_to_updated_kernel_context(dev_priv, oa_config);
 	if (ret)
-		goto out;
+		return ret;
 
 	/*
 	 * The OA register config is setup through the context image. This image
@@ -1782,7 +1782,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
 	 */
 	ret = i915_gem_wait_for_idle(dev_priv, wait_flags);
 	if (ret)
-		goto out;
+		return ret;
 
 	/* Update all contexts now that we've stalled the submission. */
 	list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
@@ -1794,10 +1794,8 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
 			continue;
 
 		regs = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
-		if (IS_ERR(regs)) {
-			ret = PTR_ERR(regs);
-			goto out;
-		}
+		if (IS_ERR(regs))
+			return PTR_ERR(regs);
 
 		ce->state->obj->mm.dirty = true;
 		regs += LRC_STATE_PN * PAGE_SIZE / sizeof(*regs);
@@ -1807,7 +1805,6 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
 		i915_gem_object_unpin_map(ce->state->obj);
 	}
 
- out:
 	return ret;
 }
 
-- 
2.17.0

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  parent reply	other threads:[~2018-05-14 15:56 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-14 15:55 [PATCH v5 0/7] drm/i915: per context slice/subslice powergating Lionel Landwerlin
2018-05-14 15:55 ` [PATCH v5 1/7] drm/i915: Program RPCS for Broadwell Lionel Landwerlin
2018-05-14 15:55 ` [PATCH v5 2/7] drm/i915: Record the sseu configuration per-context & engine Lionel Landwerlin
2018-05-14 15:55 ` Lionel Landwerlin [this message]
2018-05-14 15:55 ` [PATCH v5 4/7] drm/i915/perf: reuse intel_lrc ctx regs macro Lionel Landwerlin
2018-05-14 15:55 ` [PATCH v5 5/7] drm/i915/perf: lock powergating configuration to default when active Lionel Landwerlin
2018-05-14 15:55 ` [PATCH v5 6/7] drm/i915: count powergating transitions per engine Lionel Landwerlin
2018-05-14 15:56 ` [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace Lionel Landwerlin
2018-05-15  9:05   ` Tvrtko Ursulin
2018-05-16 15:40     ` Tvrtko Ursulin
2018-05-16 15:44       ` Lionel Landwerlin
2018-05-16 15:51       ` Chris Wilson
2018-05-21 13:22     ` Lionel Landwerlin
2018-05-21 16:00       ` Tvrtko Ursulin
2018-05-21 16:14         ` Lionel Landwerlin
2018-05-22 16:11         ` Lionel Landwerlin
2018-05-22 16:13           ` Lionel Landwerlin
2018-05-14 16:10 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: per context slice/subslice powergating (rev4) Patchwork
2018-05-14 16:12 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-14 16:33 ` ✓ Fi.CI.BAT: success " Patchwork

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