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From: Thomas Garnier <thgarnie@google.com>
To: kernel-hardening@lists.openwall.com
Cc: "Thomas Garnier" <thgarnie@google.com>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Ingo Molnar" <mingo@redhat.com>,
	"H. Peter Anvin" <hpa@zytor.com>,
	x86@kernel.org, "Matthias Kaehlcke" <mka@chromium.org>,
	"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Tom Lendacky" <thomas.lendacky@amd.com>,
	"Cao jin" <caoj.fnst@cn.fujitsu.com>,
	"Kees Cook" <keescook@chromium.org>,
	"Baoquan He" <bhe@redhat.com>, "H.J. Lu" <hjl.tools@gmail.com>,
	"Jan H. Schönherr" <jschoenh@amazon.de>,
	"Kate Stewart" <kstewart@linuxfoundation.org>,
	"Josh Poimboeuf" <jpoimboe@redhat.com>,
	"Borislav Petkov" <bp@suse.de>,
	"Dave Hansen" <dave.hansen@linux.intel.com>,
	linux-kernel@vger.kernel.org
Subject: [PATCH v5 27/27] x86/kaslr: Add option to extend KASLR range from 1GB to 3GB
Date: Mon, 25 Jun 2018 15:39:15 -0700	[thread overview]
Message-ID: <20180625224014.134829-28-thgarnie@google.com> (raw)
In-Reply-To: <20180625224014.134829-1-thgarnie@google.com>

Add a new CONFIG_RANDOMIZE_BASE_LARGE option to benefit from PIE
support. It increases the KASLR range from 1GB to 3GB. The new range
stars at 0xffffffff00000000 just above the EFI memory region. This
option is off by default.

The boot code is adapted to create the appropriate page table spanning
three PUD pages.

The relocation table uses 64-bit integers generated with the updated
relocation tool with the large-reloc option.

Signed-off-by: Thomas Garnier <thgarnie@google.com>
---
 arch/x86/Kconfig                     | 21 +++++++++++++++++++++
 arch/x86/boot/compressed/Makefile    |  5 +++++
 arch/x86/boot/compressed/misc.c      | 10 +++++++++-
 arch/x86/include/asm/page_64_types.h |  9 +++++++++
 arch/x86/kernel/head64.c             | 15 ++++++++++++---
 arch/x86/kernel/head_64.S            | 11 ++++++++++-
 6 files changed, 66 insertions(+), 5 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 42f77aff5df1..f6cb20a66e8a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -2236,6 +2236,27 @@ config X86_PIE
 	select DYNAMIC_MODULE_BASE
 	select MODULE_REL_CRCS if MODVERSIONS
 
+config RANDOMIZE_BASE_LARGE
+	bool "Increase the randomization range of the kernel image"
+	depends on X86_64 && RANDOMIZE_BASE
+	select X86_PIE
+	select X86_MODULE_PLTS if MODULES
+	default n
+	---help---
+	  Build the kernel as a Position Independent Executable (PIE) and
+	  increase the available randomization range from 1GB to 3GB.
+
+	  This option impacts performance on kernel CPU intensive workloads up
+	  to 10% due to PIE generated code. Impact on user-mode processes and
+	  typical usage would be significantly less (0.50% when you build the
+	  kernel).
+
+	  The kernel and modules will generate slightly more assembly (1 to 2%
+	  increase on the .text sections). The vmlinux binary will be
+	  significantly smaller due to less relocations.
+
+	  If unsure say N
+
 config HOTPLUG_CPU
 	bool "Support for hot-pluggable CPUs"
 	depends on SMP
diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile
index fa42f895fdde..8497ebd5e078 100644
--- a/arch/x86/boot/compressed/Makefile
+++ b/arch/x86/boot/compressed/Makefile
@@ -116,7 +116,12 @@ $(obj)/vmlinux.bin: vmlinux FORCE
 
 targets += $(patsubst $(obj)/%,%,$(vmlinux-objs-y)) vmlinux.bin.all vmlinux.relocs
 
+# Large randomization require bigger relocation table
+ifeq ($(CONFIG_RANDOMIZE_BASE_LARGE),y)
+CMD_RELOCS = arch/x86/tools/relocs --large-reloc
+else
 CMD_RELOCS = arch/x86/tools/relocs
+endif
 quiet_cmd_relocs = RELOCS  $@
       cmd_relocs = $(CMD_RELOCS) $< > $@;$(CMD_RELOCS) --abs-relocs $<
 $(obj)/vmlinux.relocs: vmlinux FORCE
diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c
index 8dd1d5ccae58..28d17bd5bad8 100644
--- a/arch/x86/boot/compressed/misc.c
+++ b/arch/x86/boot/compressed/misc.c
@@ -171,10 +171,18 @@ void __puthex(unsigned long value)
 }
 
 #if CONFIG_X86_NEED_RELOCS
+
+/* Large randomization go lower than -2G and use large relocation table */
+#ifdef CONFIG_RANDOMIZE_BASE_LARGE
+typedef long rel_t;
+#else
+typedef int rel_t;
+#endif
+
 static void handle_relocations(void *output, unsigned long output_len,
 			       unsigned long virt_addr)
 {
-	int *reloc;
+	rel_t *reloc;
 	unsigned long delta, map, ptr;
 	unsigned long min_addr = (unsigned long)output;
 	unsigned long max_addr = min_addr + (VO___bss_start - VO__text);
diff --git a/arch/x86/include/asm/page_64_types.h b/arch/x86/include/asm/page_64_types.h
index 6afac386a434..4a9f5ad945b4 100644
--- a/arch/x86/include/asm/page_64_types.h
+++ b/arch/x86/include/asm/page_64_types.h
@@ -46,7 +46,11 @@
 #define __PAGE_OFFSET           __PAGE_OFFSET_BASE_L4
 #endif /* CONFIG_DYNAMIC_MEMORY_LAYOUT */
 
+#ifdef CONFIG_RANDOMIZE_BASE_LARGE
+#define __START_KERNEL_map	_AC(0xffffffff00000000, UL)
+#else
 #define __START_KERNEL_map	_AC(0xffffffff80000000, UL)
+#endif /* CONFIG_RANDOMIZE_BASE_LARGE */
 
 /* See Documentation/x86/x86_64/mm.txt for a description of the memory map. */
 
@@ -64,9 +68,14 @@
  * 512MiB by default, leaving 1.5GiB for modules once the page tables
  * are fully set up. If kernel ASLR is configured, it can extend the
  * kernel page table mapping, reducing the size of the modules area.
+ * On PIE, we relocate the binary 2G lower so add this extra space.
  */
 #if defined(CONFIG_RANDOMIZE_BASE)
+#ifdef CONFIG_RANDOMIZE_BASE_LARGE
+#define KERNEL_IMAGE_SIZE	(_AC(3, UL) * 1024 * 1024 * 1024)
+#else
 #define KERNEL_IMAGE_SIZE	(1024 * 1024 * 1024)
+#endif
 #else
 #define KERNEL_IMAGE_SIZE	(512 * 1024 * 1024)
 #endif
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index 14bbbe592772..2276198dd2bd 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -61,6 +61,7 @@ EXPORT_SYMBOL(vmemmap_base);
 #endif
 
 #define __head	__section(.head.text)
+#define pud_count(x)   (((x + (PUD_SIZE - 1)) & ~(PUD_SIZE - 1)) >> PUD_SHIFT)
 
 /* Required for read_cr3 when building as PIE */
 unsigned long __force_order;
@@ -117,6 +118,8 @@ unsigned long __head __startup_64(unsigned long physaddr,
 {
 	unsigned long load_delta, *p;
 	unsigned long pgtable_flags;
+	unsigned long level3_kernel_start, level3_kernel_count;
+	unsigned long level3_fixmap_start;
 	pgdval_t *pgd;
 	p4dval_t *p4d;
 	pudval_t *pud;
@@ -148,6 +151,11 @@ unsigned long __head __startup_64(unsigned long physaddr,
 	/* Include the SME encryption mask in the fixup value */
 	load_delta += sme_get_me_mask();
 
+	/* Look at the randomization spread to adapt page table used */
+	level3_kernel_start = pud_index(__START_KERNEL_map);
+	level3_kernel_count = pud_count(KERNEL_IMAGE_SIZE);
+	level3_fixmap_start = level3_kernel_start + level3_kernel_count;
+
 	/* Fixup the physical addresses in the page table */
 
 	pgd = fixup_pointer(&early_top_pgt, physaddr);
@@ -164,8 +172,9 @@ unsigned long __head __startup_64(unsigned long physaddr,
 	}
 
 	pud = fixup_pointer(&level3_kernel_pgt, physaddr);
-	pud[510] += load_delta;
-	pud[511] += load_delta;
+	for (i = 0; i < level3_kernel_count; i++)
+		pud[level3_kernel_start + i] += load_delta;
+	pud[level3_fixmap_start] += load_delta;
 
 	pmd = fixup_pointer(level2_fixmap_pgt, physaddr);
 	pmd[506] += load_delta;
@@ -223,7 +232,7 @@ unsigned long __head __startup_64(unsigned long physaddr,
 	 */
 
 	pmd = fixup_pointer(level2_kernel_pgt, physaddr);
-	for (i = 0; i < PTRS_PER_PMD; i++) {
+	for (i = 0; i < PTRS_PER_PMD * level3_kernel_count; i++) {
 		if (pmd[i] & _PAGE_PRESENT)
 			pmd[i] += load_delta;
 	}
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index fddeb3d81aa6..487227d297e8 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -41,12 +41,16 @@
 
 #define l4_index(x)	(((x) >> 39) & 511)
 #define pud_index(x)	(((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
+#define pud_count(x)   (((x + (PUD_SIZE - 1)) & ~(PUD_SIZE - 1)) >> PUD_SHIFT)
 
 L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
 L4_START_KERNEL = l4_index(__START_KERNEL_map)
 
 L3_START_KERNEL = pud_index(__START_KERNEL_map)
 
+/* Adapt page table L3 space based on range of randomization */
+L3_KERNEL_ENTRY_COUNT = pud_count(KERNEL_IMAGE_SIZE)
+
 	.text
 	__HEAD
 	.code64
@@ -431,7 +435,12 @@ NEXT_PAGE(level4_kernel_pgt)
 NEXT_PAGE(level3_kernel_pgt)
 	.fill	L3_START_KERNEL,8,0
 	/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
-	.quad	level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
+	i = 0
+	.rept	L3_KERNEL_ENTRY_COUNT
+	.quad	level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC \
+		+ PAGE_SIZE*i
+	i = i + 1
+	.endr
 	.quad	level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
 
 NEXT_PAGE(level2_kernel_pgt)
-- 
2.18.0.rc2.346.g013aa6912e-goog


  parent reply	other threads:[~2018-06-25 22:43 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-25 22:38 [PATCH v5 00/27] x86: PIE support and option to extend KASLR randomization Thomas Garnier via Virtualization
2018-06-25 22:38 ` Thomas Garnier
2018-06-25 22:38 ` [PATCH v5 01/27] x86/crypto: Adapt assembly for PIE support Thomas Garnier
2018-06-25 22:38 ` [PATCH v5 02/27] x86: Use symbol name on bug table " Thomas Garnier
2018-06-25 22:38 ` [PATCH v5 03/27] x86: Use symbol name in jump " Thomas Garnier
2018-06-25 22:38 ` [PATCH v5 04/27] x86: Add macro to get symbol address " Thomas Garnier
2018-06-25 22:38 ` [PATCH v5 05/27] x86: relocate_kernel - Adapt assembly " Thomas Garnier
2018-06-25 22:38 ` [PATCH v5 06/27] x86/entry/64: " Thomas Garnier
2018-06-25 22:38 ` [PATCH v5 07/27] x86: pm-trace - " Thomas Garnier
2018-06-25 22:38 ` [PATCH v5 08/27] x86/CPU: " Thomas Garnier
2018-06-25 22:38 ` [PATCH v5 09/27] x86/acpi: " Thomas Garnier
2018-06-25 22:38 ` [PATCH v5 10/27] x86/boot/64: " Thomas Garnier
2018-06-25 22:38 ` [PATCH v5 11/27] x86/power/64: " Thomas Garnier
2018-06-25 22:39 ` [PATCH v5 12/27] x86/paravirt: " Thomas Garnier
2018-06-25 22:39 ` Thomas Garnier via Virtualization
2018-06-25 22:39 ` [PATCH v5 13/27] x86/boot/64: Build head64.c as mcmodel large when PIE is enabled Thomas Garnier
2018-06-25 22:39 ` [PATCH v5 14/27] x86/percpu: Adapt percpu for PIE support Thomas Garnier
2018-06-25 22:39 ` Thomas Garnier
2018-06-25 22:39 ` [PATCH v5 15/27] compiler: Option to default to hidden symbols Thomas Garnier
2018-06-25 22:39   ` Thomas Garnier
2018-06-25 23:25   ` Randy Dunlap
2018-06-25 23:25     ` Randy Dunlap
2018-06-25 22:39 ` [PATCH v5 16/27] compiler: Option to add PROVIDE_HIDDEN replacement for weak symbols Thomas Garnier
2018-06-25 22:39 ` [PATCH v5 17/27] x86/relocs: Handle PIE relocations Thomas Garnier
2018-06-25 22:39 ` [PATCH v5 18/27] xen: Adapt assembly for PIE support Thomas Garnier
2018-06-25 22:39   ` Thomas Garnier
2018-06-25 22:39 ` [PATCH v5 19/27] kvm: " Thomas Garnier
2018-06-25 22:39 ` [PATCH v5 20/27] x86: Support global stack cookie Thomas Garnier
2018-06-25 22:39 ` [PATCH v5 21/27] x86/ftrace: Adapt function tracing for PIE support Thomas Garnier
2018-06-26 15:21   ` Steven Rostedt
2018-06-25 22:39 ` [PATCH v5 22/27] x86/modules: Add option to start module section after kernel Thomas Garnier
2018-06-25 22:39   ` Thomas Garnier
2018-06-25 22:39 ` [PATCH v5 23/27] x86/modules: Adapt module loading for PIE support Thomas Garnier
2018-06-25 23:51   ` Randy Dunlap
2018-06-25 23:53     ` Thomas Garnier
2018-06-25 22:39 ` [PATCH v5 24/27] x86/mm: Make the x86 GOT read-only Thomas Garnier
2018-06-25 22:39 ` [PATCH v5 25/27] x86/pie: Add option to build the kernel as PIE Thomas Garnier
2018-06-25 22:39 ` [PATCH v5 26/27] x86/relocs: Add option to generate 64-bit relocations Thomas Garnier
2018-06-25 22:39 ` Thomas Garnier [this message]
2018-06-25 23:41   ` [PATCH v5 27/27] x86/kaslr: Add option to extend KASLR range from 1GB to 3GB Randy Dunlap

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