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From: martin.blumenstingl@googlemail.com (Martin Blumenstingl)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/3] ARM: dts: meson8b: add the ARM TWD timer
Date: Sat, 21 Jul 2018 19:37:21 +0200	[thread overview]
Message-ID: <20180721173721.31361-4-martin.blumenstingl@googlemail.com> (raw)
In-Reply-To: <20180721173721.31361-1-martin.blumenstingl@googlemail.com>

The Meson8B SoC is using four ARM Cortex-A5 cores which come with a
"TWD" (Timer-Watchdog) based timer. This adds support for the ARM TWD
Timer on this SoC.

Suggested-by: Carlo Caione <carlo@endlessm.com>
[ rebased patch from Carlo, use IRQ_TYPE_EDGE_RISING instead of
  IRQ_TYPE_LEVEL_LOW to prevent "GIC: PPI13 is secure or misconfigured"
  message during boot, use pre-processor macros to specify the IRQ,
  dropped TWD watchdog node since there's no driver for it anymore ]
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8b.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 08f7f6be7254..d0443ae03c72 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -117,6 +117,13 @@
 		compatible = "arm,cortex-a5-scu";
 		reg = <0xc4300000 0x100>;
 	};
+
+	timer at c4300600 {
+		compatible = "arm,cortex-a5-twd-timer";
+		reg = <0xc4300600 0x20>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+		clocks = <&clkc CLKID_CPU_DIV16>;
+	};
 }; /* end of / */
 
 &aobus {
-- 
2.18.0

WARNING: multiple messages have this Message-ID (diff)
From: martin.blumenstingl@googlemail.com (Martin Blumenstingl)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 3/3] ARM: dts: meson8b: add the ARM TWD timer
Date: Sat, 21 Jul 2018 19:37:21 +0200	[thread overview]
Message-ID: <20180721173721.31361-4-martin.blumenstingl@googlemail.com> (raw)
In-Reply-To: <20180721173721.31361-1-martin.blumenstingl@googlemail.com>

The Meson8B SoC is using four ARM Cortex-A5 cores which come with a
"TWD" (Timer-Watchdog) based timer. This adds support for the ARM TWD
Timer on this SoC.

Suggested-by: Carlo Caione <carlo@endlessm.com>
[ rebased patch from Carlo, use IRQ_TYPE_EDGE_RISING instead of
  IRQ_TYPE_LEVEL_LOW to prevent "GIC: PPI13 is secure or misconfigured"
  message during boot, use pre-processor macros to specify the IRQ,
  dropped TWD watchdog node since there's no driver for it anymore ]
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8b.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 08f7f6be7254..d0443ae03c72 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -117,6 +117,13 @@
 		compatible = "arm,cortex-a5-scu";
 		reg = <0xc4300000 0x100>;
 	};
+
+	timer at c4300600 {
+		compatible = "arm,cortex-a5-twd-timer";
+		reg = <0xc4300600 0x20>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+		clocks = <&clkc CLKID_CPU_DIV16>;
+	};
 }; /* end of / */
 
 &aobus {
-- 
2.18.0

  parent reply	other threads:[~2018-07-21 17:37 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-21 17:37 [PATCH 0/3] Meson8/Meson8b: add the ARM TWD timer Martin Blumenstingl
2018-07-21 17:37 ` Martin Blumenstingl
2018-07-21 17:37 ` [PATCH 1/3] ARM: meson: select HAVE_ARM_TWD when SMP support is enabled Martin Blumenstingl
2018-07-21 17:37   ` Martin Blumenstingl
2018-07-21 17:37 ` [PATCH 2/3] ARM: dts: meson8: add the ARM TWD timer Martin Blumenstingl
2018-07-21 17:37   ` Martin Blumenstingl
2018-07-21 17:37 ` Martin Blumenstingl [this message]
2018-07-21 17:37   ` [PATCH 3/3] ARM: dts: meson8b: " Martin Blumenstingl
2018-07-21 18:58 ` [PATCH 0/3] Meson8/Meson8b: " Martin Blumenstingl
2018-07-21 18:58   ` Martin Blumenstingl

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