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From: Michal Wajdeczko <michal.wajdeczko@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 10/21] drm/i915: Add hooks for (per-engine) context allocation/update/free
Date: Wed, 29 Aug 2018 19:18:05 +0000	[thread overview]
Message-ID: <20180829191814.10872-1-michal.wajdeczko@intel.com> (raw)
In-Reply-To: <20180829191056.63760-1-michal.wajdeczko@intel.com>

In upcoming GuC patch we will require notification per engine context
allocation/update/free to correctly setup GuC stage descriptors.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Michal Winiarski <michal.winiarski@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         | 11 +++++++++++
 drivers/gpu/drm/i915/i915_gem_context.c |  6 +++++-
 drivers/gpu/drm/i915/intel_lrc.c        |  7 +++++++
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 34f5495..234c819 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1881,6 +1881,17 @@ struct drm_i915_private {
 #define MAX_GUC_CONTEXT_HW_ID			(1 << 20) /* exclusive */
 #define GEN11_MAX_CONTEXT_HW_ID			(1 << 11) /* exclusive */
 #define GEN11_MAX_CONTEXT_HW_ID_WITH_GUC	(GEN11_MAX_CONTEXT_HW_ID - 16)
+
+		/*
+		 * Hooks for context (per-engine context, not gem context)
+		 * allocation, deallocation and descriptor update.
+		 */
+		void (*alloc_hook)(struct i915_gem_context *ctx,
+				   struct intel_engine_cs *engine);
+		void (*update_hook)(struct i915_gem_context *ctx,
+				    struct intel_engine_cs *engine);
+		void (*free_hook)(struct i915_gem_context *ctx,
+				  struct intel_engine_cs *engine);
 	} contexts;
 
 	u32 fdi_rx_config;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index e3b500c..976941e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -126,9 +126,13 @@ static void i915_gem_context_free(struct i915_gem_context *ctx)
 
 	for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {
 		struct intel_context *ce = &ctx->__engine[n];
+		struct intel_engine_cs *engine = ctx->i915->engine[n];
 
-		if (ce->ops)
+		if (ce->ops) {
+			if (ctx->i915->contexts.free_hook)
+				ctx->i915->contexts.free_hook(ctx, engine);
 			ce->ops->destroy(ce);
+		}
 	}
 
 	kfree(ctx->name);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3001a14..ef4d491 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -266,6 +266,9 @@ static inline bool need_preempt(const struct intel_engine_cs *engine,
 	}
 
 	ce->lrc_desc = desc;
+
+	if (ctx->i915->contexts.update_hook)
+		ctx->i915->contexts.update_hook(ctx, engine);
 }
 
 static struct i915_priolist *
@@ -2722,6 +2725,7 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
 					    struct intel_engine_cs *engine,
 					    struct intel_context *ce)
 {
+	struct drm_i915_private *i915 = engine->i915;
 	struct drm_i915_gem_object *ctx_obj;
 	struct i915_vma *vma;
 	uint32_t context_size;
@@ -2777,6 +2781,9 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
 		ce->sw_counter = engine->instance;
 	}
 
+	if (i915->contexts.alloc_hook)
+		i915->contexts.alloc_hook(ctx, engine);
+
 	return 0;
 
 error_ring_free:
-- 
1.9.1

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  parent reply	other threads:[~2018-08-29 19:18 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-29 19:10 [PATCH 00/21] New GuC ABI Michal Wajdeczko
2018-08-29 19:10 ` [PATCH 01/21] drm/i915/guc: Update GuC power domain states Michal Wajdeczko
2018-08-29 20:57   ` Daniele Ceraolo Spurio
2018-08-29 22:43     ` Michal Wajdeczko
2018-08-29 19:10 ` [PATCH 02/21] drm/i915/guc: Don't allow GuC submission on pre-Gen11 Michal Wajdeczko
2018-08-29 19:16   ` Srivatsa, Anusha
2018-08-30 22:58   ` John Spotswood
2018-09-06  8:28   ` Joonas Lahtinen
2018-09-06  8:29   ` Joonas Lahtinen
2018-08-29 19:10 ` [PATCH 03/21] drm/i915/guc: Simplify preparation of GuC parameter block Michal Wajdeczko
2018-08-30 22:58   ` John Spotswood
2018-09-06  8:32   ` Joonas Lahtinen
2018-08-29 19:10 ` [PATCH 04/21] drm/i915/guc: Support dual Gen9/Gen11 parameters block Michal Wajdeczko
2018-08-30 22:58   ` John Spotswood
2018-09-06  8:39   ` Joonas Lahtinen
2018-08-29 19:10 ` [PATCH 05/21] drm/i915/guc: Update sample-forcewake command Michal Wajdeczko
2018-08-29 21:52   ` Daniele Ceraolo Spurio
2018-08-29 22:31     ` Michal Wajdeczko
2018-08-29 19:10 ` [PATCH 06/21] drm/i915/guc: Use guc_class instead of engine_class in fw interface Michal Wajdeczko
2018-08-29 19:58   ` Michel Thierry
2018-08-30  0:16     ` Lionel Landwerlin
2018-08-30 13:29       ` Lis, Tomasz
2018-08-30 14:16         ` Lis, Tomasz
2018-08-30 14:56         ` Lionel Landwerlin
2018-08-30 22:34       ` Daniele Ceraolo Spurio
2018-09-06  8:55   ` Joonas Lahtinen
2018-08-29 19:15 ` [PATCH 07/21] drm/i915/guc: New GuC ADS object definition Michal Wajdeczko
2018-08-29 19:16 ` [PATCH 08/21] drm/i915/guc: Make use of the SW counter field in the context descriptor Michal Wajdeczko
2018-08-30  0:08   ` Lionel Landwerlin
2018-08-30 14:15     ` Lis, Tomasz
2018-08-31 15:31       ` Lis, Tomasz
2018-08-29 19:17 ` [PATCH 09/21] drm/i915/guc: New GuC IDs based on engine class and instance Michal Wajdeczko
2018-08-29 19:18 ` Michal Wajdeczko [this message]
2018-08-29 19:18   ` [PATCH 11/21] drm/i915/guc: New GuC stage descriptors Michal Wajdeczko
2018-08-29 23:14     ` Daniele Ceraolo Spurio
2018-10-12 18:25     ` [RFC] " Daniele Ceraolo Spurio
2018-10-17 18:42       ` Lis, Tomasz
2018-10-18 21:07         ` Daniele Ceraolo Spurio
2018-08-29 19:18   ` [PATCH 12/21] drm/i915/guc: New GuC workqueue item submission mechanism Michal Wajdeczko
2018-08-29 19:18   ` [PATCH 13/21] drm/i915/guc: Add support for resume-parsing wq item Michal Wajdeczko
2018-08-29 19:18   ` [PATCH 14/21] drm/i915/guc: New reset-engine command Michal Wajdeczko
2018-08-29 19:18   ` [PATCH 15/21] drm/i915/guc: Support for extended GuC notification messages Michal Wajdeczko
2018-08-29 19:18   ` [PATCH 16/21] drm/i915/guc: New engine-reset-complete message Michal Wajdeczko
2018-08-29 19:18   ` [PATCH 17/21] drm/i915/guc: New GuC interrupt register for Gen11 Michal Wajdeczko
2018-08-29 19:18   ` [PATCH 18/21] drm/i915/guc: New GuC scratch registers " Michal Wajdeczko
2018-08-29 19:18   ` [PATCH 19/21] drm/i915/huc: New HuC status register " Michal Wajdeczko
2018-08-30 22:59     ` John Spotswood
2018-08-29 19:19 ` [PATCH 20/21] drm/i915/guc: Enable command transport buffers " Michal Wajdeczko
2018-08-29 19:19   ` [PATCH 21/21] HAX Don't enable GuC submission on pre-Gen11 even if forced Michal Wajdeczko

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