From: Paul Cercueil <paul@crapouillou.net> To: Vinod Koul <vkoul@kernel.org>, Ralf Baechle <ralf@linux-mips.org>, Paul Burton <paul.burton@mips.com> Cc: od@zcrc.me, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Paul Cercueil <paul@crapouillou.net> Subject: [v5,09/18] dmaengine: dma-jz4780: Add support for the JZ4725B SoC Date: Wed, 29 Aug 2018 23:32:51 +0200 [thread overview] Message-ID: <20180829213300.22829-10-paul@crapouillou.net> (raw) The JZ4725B has one DMA core starring six DMA channels. As for the JZ4770, each DMA channel's clock can be enabled with a register write, the difference here being that once started, it is not possible to turn it off. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: Mathieu Malaterre <malat@debian.org> Reviewed-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> --- Notes: v2: - Add comments about channel enabling/disabling - The documentation update is now in patch 01/17 v3: No change v4: Drop the SoC version ID and use the 'flags' field of the jz4780_dma_soc_data structure v5: No change drivers/dma/dma-jz4780.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c index 2d194dfa697e..565971c2a33c 100644 --- a/drivers/dma/dma-jz4780.c +++ b/drivers/dma/dma-jz4780.c @@ -94,6 +94,7 @@ #define JZ_SOC_DATA_ALLOW_LEGACY_DT BIT(0) #define JZ_SOC_DATA_PROGRAMMABLE_DMA BIT(1) #define JZ_SOC_DATA_PER_CHAN_PM BIT(2) +#define JZ_SOC_DATA_NO_DCKES_DCKEC BIT(3) /** * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller. @@ -208,14 +209,23 @@ static inline void jz4780_dma_ctrl_writel(struct jz4780_dma_dev *jzdma, static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma, unsigned int chn) { - if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) - jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKES, BIT(chn)); + if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) { + unsigned int reg; + + if (jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC) + reg = JZ_DMA_REG_DCKE; + else + reg = JZ_DMA_REG_DCKES; + + jz4780_dma_ctrl_writel(jzdma, reg, BIT(chn)); + } } static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev *jzdma, unsigned int chn) { - if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) + if ((jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) && + !(jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC)) jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKEC, BIT(chn)); } @@ -978,6 +988,12 @@ static const struct jz4780_dma_soc_data jz4740_dma_soc_data = { .transfer_ord_max = 5, }; +static const struct jz4780_dma_soc_data jz4725b_dma_soc_data = { + .nb_channels = 6, + .transfer_ord_max = 5, + .flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC, +}; + static const struct jz4780_dma_soc_data jz4770_dma_soc_data = { .nb_channels = 6, .transfer_ord_max = 6, @@ -992,6 +1008,7 @@ static const struct jz4780_dma_soc_data jz4780_dma_soc_data = { static const struct of_device_id jz4780_dma_dt_match[] = { { .compatible = "ingenic,jz4740-dma", .data = &jz4740_dma_soc_data }, + { .compatible = "ingenic,jz4725b-dma", .data = &jz4725b_dma_soc_data }, { .compatible = "ingenic,jz4770-dma", .data = &jz4770_dma_soc_data }, { .compatible = "ingenic,jz4780-dma", .data = &jz4780_dma_soc_data }, {},
WARNING: multiple messages have this Message-ID (diff)
From: Paul Cercueil <paul@crapouillou.net> To: Vinod Koul <vkoul@kernel.org>, Ralf Baechle <ralf@linux-mips.org>, Paul Burton <paul.burton@mips.com> Cc: od@zcrc.me, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Paul Cercueil <paul@crapouillou.net> Subject: [PATCH v5 09/18] dmaengine: dma-jz4780: Add support for the JZ4725B SoC Date: Wed, 29 Aug 2018 23:32:51 +0200 [thread overview] Message-ID: <20180829213300.22829-10-paul@crapouillou.net> (raw) In-Reply-To: <20180829213300.22829-1-paul@crapouillou.net> The JZ4725B has one DMA core starring six DMA channels. As for the JZ4770, each DMA channel's clock can be enabled with a register write, the difference here being that once started, it is not possible to turn it off. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: Mathieu Malaterre <malat@debian.org> Reviewed-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> --- Notes: v2: - Add comments about channel enabling/disabling - The documentation update is now in patch 01/17 v3: No change v4: Drop the SoC version ID and use the 'flags' field of the jz4780_dma_soc_data structure v5: No change drivers/dma/dma-jz4780.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c index 2d194dfa697e..565971c2a33c 100644 --- a/drivers/dma/dma-jz4780.c +++ b/drivers/dma/dma-jz4780.c @@ -94,6 +94,7 @@ #define JZ_SOC_DATA_ALLOW_LEGACY_DT BIT(0) #define JZ_SOC_DATA_PROGRAMMABLE_DMA BIT(1) #define JZ_SOC_DATA_PER_CHAN_PM BIT(2) +#define JZ_SOC_DATA_NO_DCKES_DCKEC BIT(3) /** * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller. @@ -208,14 +209,23 @@ static inline void jz4780_dma_ctrl_writel(struct jz4780_dma_dev *jzdma, static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma, unsigned int chn) { - if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) - jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKES, BIT(chn)); + if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) { + unsigned int reg; + + if (jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC) + reg = JZ_DMA_REG_DCKE; + else + reg = JZ_DMA_REG_DCKES; + + jz4780_dma_ctrl_writel(jzdma, reg, BIT(chn)); + } } static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev *jzdma, unsigned int chn) { - if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) + if ((jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) && + !(jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC)) jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKEC, BIT(chn)); } @@ -978,6 +988,12 @@ static const struct jz4780_dma_soc_data jz4740_dma_soc_data = { .transfer_ord_max = 5, }; +static const struct jz4780_dma_soc_data jz4725b_dma_soc_data = { + .nb_channels = 6, + .transfer_ord_max = 5, + .flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC, +}; + static const struct jz4780_dma_soc_data jz4770_dma_soc_data = { .nb_channels = 6, .transfer_ord_max = 6, @@ -992,6 +1008,7 @@ static const struct jz4780_dma_soc_data jz4780_dma_soc_data = { static const struct of_device_id jz4780_dma_dt_match[] = { { .compatible = "ingenic,jz4740-dma", .data = &jz4740_dma_soc_data }, + { .compatible = "ingenic,jz4725b-dma", .data = &jz4725b_dma_soc_data }, { .compatible = "ingenic,jz4770-dma", .data = &jz4770_dma_soc_data }, { .compatible = "ingenic,jz4780-dma", .data = &jz4780_dma_soc_data }, {}, -- 2.11.0
next reply other threads:[~2018-08-29 21:32 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-08-29 21:32 Paul Cercueil [this message] 2018-08-29 21:32 ` [PATCH v5 09/18] dmaengine: dma-jz4780: Add support for the JZ4725B SoC Paul Cercueil -- strict thread matches above, loose matches on Subject: below -- 2018-08-29 21:33 [v5,18/18] MIPS: JZ4740: DTS: Add DMA nodes Paul Cercueil 2018-08-29 21:33 ` [PATCH v5 18/18] " Paul Cercueil 2018-08-29 21:32 [v5,17/18] MIPS: JZ4770: " Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 17/18] " Paul Cercueil 2018-08-29 21:32 [v5,16/18] MIPS: JZ4780: DTS: Update DMA node to match driver changes Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 16/18] " Paul Cercueil 2018-08-29 21:32 [v5,15/18] dmaengine: dma-jz4780: Use dma_set_residue() Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 15/18] " Paul Cercueil 2018-08-29 21:32 [v5,14/18] dmaengine: dma-jz4780: Further residue status fix Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 14/18] " Paul Cercueil 2018-08-29 21:32 [v5,13/18] dmaengine: dma-jz4780: Set DTCn register explicitly Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 13/18] " Paul Cercueil 2018-08-29 21:32 [v5,12/18] dmaengine: dma-jz4780: Simplify jz4780_dma_desc_residue() Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 12/18] " Paul Cercueil 2018-08-29 21:32 [v5,11/18] dmaengine: dma-jz4780: Add missing residue DTC mask Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 11/18] " Paul Cercueil 2018-08-29 21:32 [v5,10/18] dmaengine: dma-jz4780: Enable Fast DMA to the AIC Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 10/18] " Paul Cercueil 2018-08-29 21:32 [v5,08/18] dmaengine: dma-jz4780: Add support for the JZ4740 SoC Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 08/18] " Paul Cercueil 2018-08-29 21:32 [v5,07/18] dmaengine: dma-jz4780: Add support for the JZ4770 SoC Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 07/18] " Paul Cercueil 2018-08-29 21:32 [v5,06/18] dmaengine: dma-jz4780: Don't depend on MACH_JZ4780 Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 06/18] " Paul Cercueil 2018-08-29 21:32 [v5,05/18] dmaengine: dma-jz4780: Use 4-word descriptors Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 05/18] " Paul Cercueil 2018-08-29 21:32 [v5,04/18] dmaengine: dma-jz4780: Separate chan/ctrl registers Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 04/18] " Paul Cercueil 2018-08-29 21:32 [v5,03/18] dmaengine: dma-jz4780: Avoid hardcoding number of channels Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 03/18] " Paul Cercueil 2018-08-29 21:32 [v5,02/18] dmaengine: dma-jz4780: Return error if not probed from DT Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 02/18] " Paul Cercueil 2018-08-29 21:32 [v5,01/18] dt-bindings: jz4780-dma: Update bindings to reflect driver changes Paul Cercueil 2018-08-29 21:32 ` [PATCH v5 01/18] " Paul Cercueil 2018-08-29 21:32 [PATCH v5 00/18] JZ4780 DMA patchset v5 Paul Cercueil 2018-09-11 7:29 ` Vinod
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