From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> To: dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, Ulrich Hecht <uli@fpond.eu>, Kieran Bingham <kieran.bingham@ideasonboard.com> Subject: [PATCH v2 10/16] drm: rcar-du: Don't use TV sync mode when not supported by the hardware Date: Fri, 14 Sep 2018 12:10:40 +0300 [thread overview] Message-ID: <20180914091046.483-11-laurent.pinchart+renesas@ideasonboard.com> (raw) In-Reply-To: <20180914091046.483-1-laurent.pinchart+renesas@ideasonboard.com> The official way to stop the display is to clear the display enable (DEN) bit in the DSYSR register, but that operates at a group level and affects the two channels in the group. To disable channels selectively, the driver uses TV sync mode that stops display operation on the channel and turns output signals into inputs. While TV sync mode is available in all DU models currently supported, the D3 and E3 DUs don't support it. We will thus need to find an alternative way to turn channels off. In the meantime, condition the switch to TV sync mode to the availability of the feature, to avoid writing an invalid value to the DSYSR register. The display output will turn blank as all planes are disabled when stopping the CRTC. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org> --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 7 ++++++- drivers/gpu/drm/rcar-du/rcar_du_drv.c | 33 ++++++++++++++++++++++----------- drivers/gpu/drm/rcar-du/rcar_du_drv.h | 1 + 3 files changed, 29 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index f827fccf6416..17741843cf51 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -643,8 +643,13 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc) /* * Select switch sync mode. This stops display operation and configures * the HSYNC and VSYNC signals as inputs. + * + * TODO: Find another way to stop the display for DUs that don't support + * TVM sync. */ - rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH); + if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_TVM_SYNC)) + rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK, + DSYSR_TVM_SWITCH); rcar_du_group_start_stop(rcrtc->group, false); } diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index 0954ecd2f943..fa0d381c2d0f 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -36,7 +36,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = { .gen = 2, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(1) | BIT(0), .routes = { /* @@ -58,7 +59,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = { .gen = 2, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(1) | BIT(0), .routes = { /* @@ -77,7 +79,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = { static const struct rcar_du_device_info rcar_du_r8a7779_info = { .gen = 2, - .features = RCAR_DU_FEATURE_INTERLACED, + .features = RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(1) | BIT(0), .routes = { /* @@ -99,7 +102,8 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = { .gen = 2, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .quirks = RCAR_DU_QUIRK_ALIGN_128B, .channels_mask = BIT(2) | BIT(1) | BIT(0), .routes = { @@ -128,7 +132,8 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = { .gen = 2, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(1) | BIT(0), .routes = { /* @@ -151,7 +156,8 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = { .gen = 2, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(1) | BIT(0), .routes = { /* R8A7792 has two RGB outputs. */ @@ -170,7 +176,8 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = { .gen = 2, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(1) | BIT(0), .routes = { /* @@ -193,7 +200,8 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = { .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS | RCAR_DU_FEATURE_VSP1_SOURCE - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0), .routes = { /* @@ -226,7 +234,8 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = { .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS | RCAR_DU_FEATURE_VSP1_SOURCE - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(2) | BIT(1) | BIT(0), .routes = { /* @@ -255,7 +264,8 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = { .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS | RCAR_DU_FEATURE_VSP1_SOURCE - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(3) | BIT(1) | BIT(0), .routes = { /* @@ -284,7 +294,8 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = { .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS | RCAR_DU_FEATURE_VSP1_SOURCE - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(0), .routes = { /* R8A77970 has one RGB output and one LVDS output. */ diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h index ebba9aefba6a..143c037e2c0f 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h @@ -27,6 +27,7 @@ struct rcar_du_device; #define RCAR_DU_FEATURE_EXT_CTRL_REGS BIT(1) /* Has extended control registers */ #define RCAR_DU_FEATURE_VSP1_SOURCE BIT(2) /* Has inputs from VSP1 */ #define RCAR_DU_FEATURE_INTERLACED BIT(3) /* HW supports interlaced */ +#define RCAR_DU_FEATURE_TVM_SYNC BIT(4) /* Has TV switch/sync modes */ #define RCAR_DU_QUIRK_ALIGN_128B BIT(0) /* Align pitches to 128 bytes */ -- Regards, Laurent Pinchart
WARNING: multiple messages have this Message-ID (diff)
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> To: dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, Ulrich Hecht <uli@fpond.eu>, Kieran Bingham <kieran.bingham@ideasonboard.com> Subject: [PATCH v2 10/16] drm: rcar-du: Don't use TV sync mode when not supported by the hardware Date: Fri, 14 Sep 2018 12:10:40 +0300 [thread overview] Message-ID: <20180914091046.483-11-laurent.pinchart+renesas@ideasonboard.com> (raw) In-Reply-To: <20180914091046.483-1-laurent.pinchart+renesas@ideasonboard.com> The official way to stop the display is to clear the display enable (DEN) bit in the DSYSR register, but that operates at a group level and affects the two channels in the group. To disable channels selectively, the driver uses TV sync mode that stops display operation on the channel and turns output signals into inputs. While TV sync mode is available in all DU models currently supported, the D3 and E3 DUs don't support it. We will thus need to find an alternative way to turn channels off. In the meantime, condition the switch to TV sync mode to the availability of the feature, to avoid writing an invalid value to the DSYSR register. The display output will turn blank as all planes are disabled when stopping the CRTC. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org> --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 7 ++++++- drivers/gpu/drm/rcar-du/rcar_du_drv.c | 33 ++++++++++++++++++++++----------- drivers/gpu/drm/rcar-du/rcar_du_drv.h | 1 + 3 files changed, 29 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index f827fccf6416..17741843cf51 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -643,8 +643,13 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc) /* * Select switch sync mode. This stops display operation and configures * the HSYNC and VSYNC signals as inputs. + * + * TODO: Find another way to stop the display for DUs that don't support + * TVM sync. */ - rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH); + if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_TVM_SYNC)) + rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK, + DSYSR_TVM_SWITCH); rcar_du_group_start_stop(rcrtc->group, false); } diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index 0954ecd2f943..fa0d381c2d0f 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -36,7 +36,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = { .gen = 2, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(1) | BIT(0), .routes = { /* @@ -58,7 +59,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = { .gen = 2, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(1) | BIT(0), .routes = { /* @@ -77,7 +79,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = { static const struct rcar_du_device_info rcar_du_r8a7779_info = { .gen = 2, - .features = RCAR_DU_FEATURE_INTERLACED, + .features = RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(1) | BIT(0), .routes = { /* @@ -99,7 +102,8 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = { .gen = 2, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .quirks = RCAR_DU_QUIRK_ALIGN_128B, .channels_mask = BIT(2) | BIT(1) | BIT(0), .routes = { @@ -128,7 +132,8 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = { .gen = 2, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(1) | BIT(0), .routes = { /* @@ -151,7 +156,8 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = { .gen = 2, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(1) | BIT(0), .routes = { /* R8A7792 has two RGB outputs. */ @@ -170,7 +176,8 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = { .gen = 2, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(1) | BIT(0), .routes = { /* @@ -193,7 +200,8 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = { .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS | RCAR_DU_FEATURE_VSP1_SOURCE - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0), .routes = { /* @@ -226,7 +234,8 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = { .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS | RCAR_DU_FEATURE_VSP1_SOURCE - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(2) | BIT(1) | BIT(0), .routes = { /* @@ -255,7 +264,8 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = { .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS | RCAR_DU_FEATURE_VSP1_SOURCE - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(3) | BIT(1) | BIT(0), .routes = { /* @@ -284,7 +294,8 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = { .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS | RCAR_DU_FEATURE_VSP1_SOURCE - | RCAR_DU_FEATURE_INTERLACED, + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, .channels_mask = BIT(0), .routes = { /* R8A77970 has one RGB output and one LVDS output. */ diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h index ebba9aefba6a..143c037e2c0f 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h @@ -27,6 +27,7 @@ struct rcar_du_device; #define RCAR_DU_FEATURE_EXT_CTRL_REGS BIT(1) /* Has extended control registers */ #define RCAR_DU_FEATURE_VSP1_SOURCE BIT(2) /* Has inputs from VSP1 */ #define RCAR_DU_FEATURE_INTERLACED BIT(3) /* HW supports interlaced */ +#define RCAR_DU_FEATURE_TVM_SYNC BIT(4) /* Has TV switch/sync modes */ #define RCAR_DU_QUIRK_ALIGN_128B BIT(0) /* Align pitches to 128 bytes */ -- Regards, Laurent Pinchart _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2018-09-14 14:24 UTC|newest] Thread overview: 118+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-09-14 9:10 [PATCH v2 00/16] R-Car D3/E3 display support (with LVDS PLL) Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-14 9:10 ` [PATCH v2 01/16] dt-bindings: display: renesas: du: Document r8a77990 bindings Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-17 10:53 ` Ulrich Hecht 2018-09-17 10:53 ` Ulrich Hecht 2018-09-14 9:10 ` [PATCH v2 02/16] dt-bindings: display: renesas: lvds: " Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-17 10:53 ` Ulrich Hecht 2018-09-17 10:53 ` Ulrich Hecht 2018-09-24 11:36 ` Kieran Bingham 2018-09-24 11:36 ` Kieran Bingham 2018-09-14 9:10 ` [PATCH v2 03/16] dt-bindings: display: renesas: lvds: Add EXTAL and DU_DOTCLKIN clocks Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-17 10:53 ` Ulrich Hecht 2018-09-17 10:53 ` Ulrich Hecht 2018-09-24 19:04 ` Kieran Bingham 2018-09-24 19:04 ` Kieran Bingham 2018-09-14 9:10 ` [PATCH v2 04/16] drm: bridge: thc63: Restrict modes based on hardware operating frequency Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-17 10:53 ` Ulrich Hecht 2018-09-17 10:53 ` Ulrich Hecht 2018-09-17 12:23 ` Laurent Pinchart 2018-09-17 12:23 ` Laurent Pinchart 2018-09-14 9:10 ` [PATCH v2 05/16] drm: rcar-du: lvds: D3/E3 support Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-17 10:53 ` Ulrich Hecht 2018-09-17 10:53 ` Ulrich Hecht 2018-09-17 12:41 ` Laurent Pinchart 2018-09-17 12:41 ` Laurent Pinchart 2018-09-17 12:49 ` jacopo mondi 2018-09-17 12:49 ` jacopo mondi 2018-09-14 9:10 ` [PATCH v2 06/16] drm: rcar-du: Perform the initial CRTC setup from rcar_du_crtc_get() Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-17 12:50 ` jacopo mondi 2018-09-17 12:50 ` jacopo mondi 2018-09-26 15:55 ` Ulrich Hecht 2018-09-26 15:55 ` Ulrich Hecht 2018-09-28 15:14 ` Laurent Pinchart 2018-09-28 15:14 ` Laurent Pinchart 2018-09-14 9:10 ` [PATCH v2 07/16] drm: rcar-du: Use LVDS PLL clock as dot clock when possible Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-17 12:55 ` jacopo mondi 2018-09-17 12:55 ` jacopo mondi 2018-09-26 15:55 ` Ulrich Hecht 2018-09-26 15:55 ` Ulrich Hecht 2018-11-27 0:44 ` Kuninori Morimoto 2018-11-27 0:44 ` Kuninori Morimoto 2018-12-06 9:50 ` Laurent Pinchart 2018-12-06 9:50 ` Laurent Pinchart 2018-12-07 1:25 ` Kuninori Morimoto 2018-12-07 1:25 ` Kuninori Morimoto 2018-09-14 9:10 ` [PATCH v2 08/16] drm: rcar-du: Enable configurable DPAD0 routing on Gen3 Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-17 12:56 ` jacopo mondi 2018-09-17 12:56 ` jacopo mondi 2018-09-26 15:55 ` Ulrich Hecht 2018-09-26 15:55 ` Ulrich Hecht 2018-09-14 9:10 ` [PATCH v2 09/16] drm: rcar-du: Cache DSYSR value to ensure known initial value Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-24 11:18 ` Kieran Bingham 2018-09-24 11:18 ` Kieran Bingham 2018-09-26 15:55 ` Ulrich Hecht 2018-09-26 15:55 ` Ulrich Hecht 2018-09-14 9:10 ` Laurent Pinchart [this message] 2018-09-14 9:10 ` [PATCH v2 10/16] drm: rcar-du: Don't use TV sync mode when not supported by the hardware Laurent Pinchart 2018-09-24 11:26 ` Kieran Bingham 2018-09-24 11:26 ` Kieran Bingham 2018-09-26 15:55 ` Ulrich Hecht 2018-09-26 15:55 ` Ulrich Hecht 2018-09-14 9:10 ` [PATCH v2 11/16] drm: rcar-du: Add r8a77990 and r8a77995 device support Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-24 11:41 ` Kieran Bingham 2018-09-24 11:41 ` Kieran Bingham 2018-09-14 9:10 ` [PATCH v2 12/16] arm64: dts: renesas: r8a77990: Add I2C device nodes Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-17 7:33 ` Simon Horman 2018-09-17 7:33 ` Simon Horman 2018-09-17 8:08 ` Laurent Pinchart 2018-09-17 8:08 ` Laurent Pinchart 2018-09-14 9:10 ` [PATCH v2 13/16] arm64: dts: renesas: r8a77990: Add display output support Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-17 7:50 ` Simon Horman 2018-09-17 7:50 ` Simon Horman 2018-09-17 8:14 ` Simon Horman 2018-09-17 8:14 ` Simon Horman 2018-09-17 8:47 ` Laurent Pinchart 2018-09-17 8:47 ` Laurent Pinchart 2018-09-17 8:54 ` Laurent Pinchart 2018-09-17 8:54 ` Laurent Pinchart 2018-09-17 8:59 ` Laurent Pinchart 2018-09-17 8:59 ` Laurent Pinchart 2018-09-19 8:35 ` Simon Horman 2018-09-19 8:35 ` Simon Horman 2018-09-19 13:11 ` Laurent Pinchart 2018-09-19 13:11 ` Laurent Pinchart 2018-09-21 7:16 ` Simon Horman 2018-09-21 7:16 ` Simon Horman 2018-09-21 8:41 ` Laurent Pinchart 2018-09-21 8:41 ` Laurent Pinchart 2018-09-17 8:38 ` Laurent Pinchart 2018-09-17 8:38 ` Laurent Pinchart 2018-09-17 8:51 ` Simon Horman 2018-09-17 8:51 ` Simon Horman 2018-09-17 9:08 ` Laurent Pinchart 2018-09-17 9:08 ` Laurent Pinchart 2018-09-17 9:48 ` Geert Uytterhoeven 2018-09-17 9:48 ` Geert Uytterhoeven 2018-09-17 10:01 ` Laurent Pinchart 2018-09-17 10:01 ` Laurent Pinchart 2018-09-14 9:10 ` [PATCH v2 14/16] arm64: dts: renesas: r8a77995: Add LVDS support Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-14 9:10 ` [PATCH v2 15/16] arm64: dts: renesas: r8a77990: ebisu: Enable VGA and HDMI outputs Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart 2018-09-26 15:55 ` Ulrich Hecht 2018-09-26 15:55 ` Ulrich Hecht 2018-09-14 9:10 ` [PATCH v2 16/16] arm64: dts: renesas: r8a77995: draak: Enable HDMI display output Laurent Pinchart 2018-09-14 9:10 ` Laurent Pinchart
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