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From: Ryan Case <ryandcase@chromium.org>
To: Mark Brown <broonie@kernel.org>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>,
	Stephen Boyd <swboyd@chromium.org>,
	Doug Anderson <dianders@chromium.org>,
	linux-arm-msm@vger.kernel.org,
	Girish Mahadevan <girishm@codeaurora.org>,
	Ryan Case <ryandcase@chromium.org>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-spi@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>
Subject: [PATCH v2 1/2] dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation
Date: Thu, 20 Sep 2018 15:40:54 -0700	[thread overview]
Message-ID: <20180920224055.164856-1-ryandcase@chromium.org> (raw)

From: Girish Mahadevan <girishm@codeaurora.org>

Bindings for Qualcomm Quad SPI used on SoCs such as sdm845.

Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Signed-off-by: Ryan Case <ryandcase@chromium.org>
---

Changes in v2:
- Added commit text
- Removed invalid property
- Updated example to match sdm845 with attached spi-nor

 .../bindings/spi/qcom,spi-qcom-qspi.txt       | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt

diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
new file mode 100644
index 000000000000..ecfb1e2bd520
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
@@ -0,0 +1,36 @@
+Qualcomm Quad Serial Peripheral Interface (QSPI)
+
+The QSPI controller allows SPI protocol communication in single, dual, or quad
+wire transmission modes for read/write access to slaves such as NOR flash.
+
+Required properties:
+- compatible:	Should contain:
+		"qcom,sdm845-qspi"
+- reg:		Should contain the base register location and length.
+- interrupts:	Interrupt number used by the controller.
+- clocks:	Should contain the core and AHB clock.
+- clock-names:	Should be "core" for core clock and "iface" for AHB clock.
+
+SPI slave nodes must be children of the SPI master node and can contain
+properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+	qspi: qspi@88df000 {
+		compatible = "qcom,sdm845-qspi";
+		reg = <0x88df000 0x600>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "iface", "core";
+		clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+			 <&gcc GCC_QSPI_CORE_CLK>;
+
+		device@0 {
+			compatible = "jedec,spi-nor";
+			reg = <0>;
+			spi-max-frequency = <25000000>;
+			spi-tx-bus-width = <2>;
+			spi-rx-bus-width = <2>;
+		};
+	};
-- 
2.19.0.444.g18242da7ef-goog

             reply	other threads:[~2018-09-20 22:40 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-20 22:40 Ryan Case [this message]
2018-09-20 22:40 ` [PATCH v2 2/2] spi: Introduce new driver for Qualcomm QuadSPI controller Ryan Case
2018-09-20 22:46   ` Randy Dunlap
2018-09-20 23:47     ` Ryan Case
2018-09-21 16:31   ` Mark Brown
2018-09-21 17:30 ` [PATCH v2 1/2] dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation Stephen Boyd
2018-09-21 17:30   ` Stephen Boyd
2018-09-21 17:39   ` Mark Brown
2018-09-21 18:33     ` Trent Piepho
2018-09-21 17:40   ` Doug Anderson
2018-09-21 18:40     ` Stephen Boyd
2018-09-21 18:48       ` Doug Anderson
2018-09-21 18:51       ` Mark Brown
2018-09-23  3:45         ` Stephen Boyd
2018-09-24 17:13           ` Doug Anderson
2018-09-24 18:23             ` Trent Piepho
2018-09-25 16:02               ` Doug Anderson

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