From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> To: linux-amlogic@lists.infradead.org, jbrunet@baylibre.com, narmstrong@baylibre.com Cc: linux-clk@vger.kernel.org, carlo@caione.org, Martin Blumenstingl <martin.blumenstingl@googlemail.com> Subject: [PATCH 2/2] clk: meson: meson8b: fix the width of the cpu_scale_div clock Date: Thu, 27 Sep 2018 10:59:21 +0200 [thread overview] Message-ID: <20180927085921.24627-3-martin.blumenstingl@googlemail.com> (raw) In-Reply-To: <20180927085921.24627-1-martin.blumenstingl@googlemail.com> According to the public S805 datasheet HHI_SYS_CPU_CLK_CNTL1[29:20] is the register for the CPU scale_div clock. This matches the code in Amlogic's 3.10 GPL kernel sources: N = (aml_read_reg32(P_HHI_SYS_CPU_CLK_CNTL1) >> 20) & 0x3FF; This means that the divider register is 10 bit wide instead of 9 bits. So far this is not a problem since all u-boot versions I have seen are not using the cpu_scale_div clock at all (instead they are configuring the CPU clock to run off cpu_in_sel directly). The fixes tag points to the latest rework of the CPU clocks. However, even before the rework it was wrong. Commit 7a29a869434e8b ("clk: meson: Add support for Meson clock controller") defines MESON_N_WIDTH as 9 (in drivers/clk/meson/clk-cpu.c). But since the old clk-cpu implementation this only carries the fixes tag for the CPU clock rewordk. Fixes: 251b6fd38bcb9c ("clk: meson: rework meson8b cpu clock") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- drivers/clk/meson/meson8b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index d3f4e11d106d..8658a662b10e 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -594,7 +594,7 @@ static struct clk_regmap meson8b_cpu_scale_div = { .data = &(struct clk_regmap_div_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, .shift = 20, - .width = 9, + .width = 10, .table = cpu_scale_table, .flags = CLK_DIVIDER_ALLOW_ZERO, }, -- 2.19.0
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From: martin.blumenstingl@googlemail.com (Martin Blumenstingl) To: linus-amlogic@lists.infradead.org Subject: [PATCH 2/2] clk: meson: meson8b: fix the width of the cpu_scale_div clock Date: Thu, 27 Sep 2018 10:59:21 +0200 [thread overview] Message-ID: <20180927085921.24627-3-martin.blumenstingl@googlemail.com> (raw) In-Reply-To: <20180927085921.24627-1-martin.blumenstingl@googlemail.com> According to the public S805 datasheet HHI_SYS_CPU_CLK_CNTL1[29:20] is the register for the CPU scale_div clock. This matches the code in Amlogic's 3.10 GPL kernel sources: N = (aml_read_reg32(P_HHI_SYS_CPU_CLK_CNTL1) >> 20) & 0x3FF; This means that the divider register is 10 bit wide instead of 9 bits. So far this is not a problem since all u-boot versions I have seen are not using the cpu_scale_div clock at all (instead they are configuring the CPU clock to run off cpu_in_sel directly). The fixes tag points to the latest rework of the CPU clocks. However, even before the rework it was wrong. Commit 7a29a869434e8b ("clk: meson: Add support for Meson clock controller") defines MESON_N_WIDTH as 9 (in drivers/clk/meson/clk-cpu.c). But since the old clk-cpu implementation this only carries the fixes tag for the CPU clock rewordk. Fixes: 251b6fd38bcb9c ("clk: meson: rework meson8b cpu clock") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- drivers/clk/meson/meson8b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index d3f4e11d106d..8658a662b10e 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -594,7 +594,7 @@ static struct clk_regmap meson8b_cpu_scale_div = { .data = &(struct clk_regmap_div_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, .shift = 20, - .width = 9, + .width = 10, .table = cpu_scale_table, .flags = CLK_DIVIDER_ALLOW_ZERO, }, -- 2.19.0
next prev parent reply other threads:[~2018-09-27 15:16 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-09-27 8:59 [PATCH 0/2] Meson8b: fixes for the cpu_scale_div clock Martin Blumenstingl 2018-09-27 8:59 ` Martin Blumenstingl 2018-09-27 8:59 ` [PATCH 1/2] clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table Martin Blumenstingl 2018-09-27 8:59 ` Martin Blumenstingl 2018-09-27 8:59 ` Martin Blumenstingl [this message] 2018-09-27 8:59 ` [PATCH 2/2] clk: meson: meson8b: fix the width of the cpu_scale_div clock Martin Blumenstingl 2018-11-08 14:16 ` [PATCH 0/2] Meson8b: fixes for " Neil Armstrong 2018-11-08 14:16 ` Neil Armstrong 2018-11-16 8:30 ` Neil Armstrong 2018-11-16 8:30 ` Neil Armstrong
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