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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org, qemu-arm@nongnu.org
Cc: peter.maydell@linaro.org, richard.henderson@linaro.org,
	frederic.konrad@adacore.com, alistair@alistair23.me,
	philmd@redhat.com, frasse.iglesias@gmail.com,
	figlesia@xilinx.com, sstabellini@kernel.org,
	sai.pavan.boddu@xilinx.com, edgar.iglesias@xilinx.com
Subject: [Qemu-devel] [PATCH v2 08/12] net: cadence_gem: Announce 64bit addressing support
Date: Thu, 11 Oct 2018 04:19:27 +0200	[thread overview]
Message-ID: <20181011021931.4249-9-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <20181011021931.4249-1-edgar.iglesias@gmail.com>

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Announce 64bit addressing support.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 hw/net/cadence_gem.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 550225c15b..7f96de4aff 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -142,6 +142,7 @@
 #define GEM_DESCONF4      (0x0000028C/4)
 #define GEM_DESCONF5      (0x00000290/4)
 #define GEM_DESCONF6      (0x00000294/4)
+#define GEM_DESCONF6_64B_MASK (1U << 23)
 #define GEM_DESCONF7      (0x00000298/4)
 
 #define GEM_INT_Q1_STATUS               (0x00000400 / 4)
@@ -1300,7 +1301,7 @@ static void gem_reset(DeviceState *d)
     s->regs[GEM_DESCONF] = 0x02500111;
     s->regs[GEM_DESCONF2] = 0x2ab13fff;
     s->regs[GEM_DESCONF5] = 0x002f2045;
-    s->regs[GEM_DESCONF6] = 0x0;
+    s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
 
     queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
     s->regs[GEM_DESCONF6] |= queues_mask;
-- 
2.17.1

  parent reply	other threads:[~2018-10-11  2:19 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-11  2:19 [Qemu-devel] [PATCH v2 00/12] arm: Add first models of Xilinx Versal SoC Edgar E. Iglesias
2018-10-11  2:19 ` [Qemu-devel] [PATCH v2 01/12] net: cadence_gem: Disable TSU feature bit Edgar E. Iglesias
2018-10-11  2:19 ` [Qemu-devel] [PATCH v2 02/12] net: cadence_gem: Announce availability of priority queues Edgar E. Iglesias
2018-10-16 16:15   ` Peter Maydell
2018-10-17 13:30     ` Edgar E. Iglesias
2018-10-11  2:19 ` [Qemu-devel] [PATCH v2 03/12] net: cadence_gem: Use uint32_t for 32bit descriptor words Edgar E. Iglesias
2018-10-11  2:19 ` [Qemu-devel] [PATCH v2 04/12] net: cadence_gem: Add macro with max number of " Edgar E. Iglesias
2018-10-11  2:19 ` [Qemu-devel] [PATCH v2 05/12] net: cadence_gem: Add support for extended descriptors Edgar E. Iglesias
2018-10-11  2:19 ` [Qemu-devel] [PATCH v2 06/12] net: cadence_gem: Add support for selecting the DMA MemoryRegion Edgar E. Iglesias
2018-10-12 17:52   ` Alistair Francis
2018-10-11  2:19 ` [Qemu-devel] [PATCH v2 07/12] net: cadence_gem: Implement support for 64bit descriptor addresses Edgar E. Iglesias
2018-10-11  2:19 ` Edgar E. Iglesias [this message]
2018-10-11  2:19 ` [Qemu-devel] [PATCH v2 09/12] target-arm: powerctl: Enable HVC when starting CPUs to EL2 Edgar E. Iglesias
2018-10-11  2:19 ` [Qemu-devel] [PATCH v2 10/12] target/arm: Add the Cortex-A72 Edgar E. Iglesias
2018-10-11  2:19 ` [Qemu-devel] [PATCH v2 11/12] hw/arm: versal: Add a model of Xilinx Versal SoC Edgar E. Iglesias
2018-10-11  2:19 ` [Qemu-devel] [PATCH v2 12/12] hw/arm: versal: Add a virtual Xilinx Versal board Edgar E. Iglesias
2018-10-16 10:53 ` [Qemu-devel] [PATCH v2 00/12] arm: Add first models of Xilinx Versal SoC Peter Maydell

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