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From: Anusha Srivatsa <anusha.srivatsa@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Manasi Navare <manasi.d.navare@intel.com>,
	Anusha Srivatsa <anusha.srivatsa@intel.com>,
	dri-devel@lists.freedesktop.org
Subject: [v5 1/6] i915/dp/fec: Cache the FEC_CAPABLE DPCD register
Date: Thu,  1 Nov 2018 22:41:54 -0700	[thread overview]
Message-ID: <20181102054159.28886-2-anusha.srivatsa@intel.com> (raw)
In-Reply-To: <20181102054159.28886-1-anusha.srivatsa@intel.com>

Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.

v2: Avoid using memset and array for a single
field. (Manasi,Jani)

v3: Print FEC CAPABILITY value. (Manasi)

Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5a638503e36a..253e063e23b0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4201,6 +4201,9 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
 	 */
 	memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
 
+	/* Clear fec_capable to avoid using stale values */
+	intel_dp->fec_capable = 0;
+
 	/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
 	    intel_dp->edp_dpcd[0] >= DP_EDP_14) {
@@ -4213,6 +4216,15 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
 		DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
 			      (int)sizeof(intel_dp->dsc_dpcd),
 			      intel_dp->dsc_dpcd);
+		/* FEC is supported only on DP 1.4 */
+		if (!intel_dp_is_edp(intel_dp)) {
+			if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
+					      &intel_dp->fec_capable) < 0)
+				DRM_ERROR("Failed to read FEC DPCD register\n");
+
+		DRM_DEBUG_KMS("FEC CAPABILITY: %x\n",
+			      intel_dp->fec_capable);
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 16bbc3768e02..9a94c6544bf5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1119,6 +1119,7 @@ struct intel_dp {
 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 	u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
+	u8 fec_capable;
 	/* source rates */
 	int num_source_rates;
 	const int *source_rates;
-- 
2.17.1

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  reply	other threads:[~2018-11-02  5:41 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-02  5:41 [v3 0/7] Forward Error Correction Anusha Srivatsa
2018-11-02  5:41 ` Anusha Srivatsa [this message]
2018-11-02  5:41 ` [v5 2/6] drm/dp/fec: DRM helper for " Anusha Srivatsa
2018-11-02  5:41 ` [v5 3/6] i915/dp/fec: Add fec_enable to the crtc state Anusha Srivatsa
2018-11-02  5:41 ` [v5 4/6] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Anusha Srivatsa
2018-11-02  5:41 ` [v5 5/6] i915/dp/fec: Configure the Forward Error Correction bits Anusha Srivatsa
2018-11-02  5:41 ` [v5 6/6] drm/i915/fec: Disable FEC state Anusha Srivatsa
2018-11-02  5:59 ` ✗ Fi.CI.BAT: failure for Forward Error Correction (rev5) Patchwork

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