From: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> To: joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, robin.murphy-5wv7dgnIgG8@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org, architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org, robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org Subject: [RESEND PATCH v17 4/5] dt-bindings: arm-smmu: Add bindings for qcom, smmu-v2 Date: Fri, 16 Nov 2018 16:54:29 +0530 [thread overview] Message-ID: <20181116112430.31248-5-vivek.gautam@codeaurora.org> (raw) In-Reply-To: <20181116112430.31248-1-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Add bindings doc for Qcom's smmu-v2 implementation. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Robin Murphy <robin.murphy@arm.com> --- .../devicetree/bindings/iommu/arm,smmu.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 8a6ffce12af5..a6504b37cc21 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -17,10 +17,16 @@ conditions. "arm,mmu-401" "arm,mmu-500" "cavium,smmu-v2" + "qcom,smmu-v2" depending on the particular implementation and/or the version of the architecture implemented. + Qcom SoCs must contain, as below, SoC-specific compatibles + along with "qcom,smmu-v2": + "qcom,msm8996-smmu-v2", "qcom,smmu-v2", + "qcom,sdm845-smmu-v2", "qcom,smmu-v2". + - reg : Base address and size of the SMMU. - #global-interrupts : The number of global interrupts exposed by the @@ -71,6 +77,22 @@ conditions. or using stream matching with #iommu-cells = <2>, and may be ignored if present in such cases. +- clock-names: List of the names of clocks input to the device. The + required list depends on particular implementation and + is as follows: + - for "qcom,smmu-v2": + - "bus": clock required for downstream bus access and + for the smmu ptw, + - "iface": clock required to access smmu's registers + through the TCU's programming interface. + - unspecified for other implementations. + +- clocks: Specifiers for all clocks listed in the clock-names property, + as per generic clock bindings. + +- power-domains: Specifiers for power domains required to be powered on for + the SMMU to operate, as per generic power domain bindings. + ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : @@ -137,3 +159,20 @@ conditions. iommu-map = <0 &smmu3 0 0x400>; ... }; + + /* Qcom's arm,smmu-v2 implementation */ + smmu4: iommu@d00000 { + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + reg = <0xd00000 0x10000>; + + #global-interrupts = <1>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc SMMU_MDP_AXI_CLK>, + <&mmcc SMMU_MDP_AHB_CLK>; + clock-names = "bus", "iface"; + }; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
WARNING: multiple messages have this Message-ID (diff)
From: Vivek Gautam <vivek.gautam@codeaurora.org> To: joro@8bytes.org, robh+dt@kernel.org, robin.murphy@arm.com, will.deacon@arm.com, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: alex.williamson@redhat.com, mark.rutland@arm.com, rjw@rjwysocki.net, robdclark@gmail.com, linux-pm@vger.kernel.org, freedreno@lists.freedesktop.org, sboyd@kernel.org, tfiga@chromium.org, jcrouse@codeaurora.org, sricharan@codeaurora.org, m.szyprowski@samsung.com, architt@codeaurora.org, linux-arm-msm@vger.kernel.org, Vivek Gautam <vivek.gautam@codeaurora.org> Subject: [RESEND PATCH v17 4/5] dt-bindings: arm-smmu: Add bindings for qcom,smmu-v2 Date: Fri, 16 Nov 2018 16:54:29 +0530 [thread overview] Message-ID: <20181116112430.31248-5-vivek.gautam@codeaurora.org> (raw) In-Reply-To: <20181116112430.31248-1-vivek.gautam@codeaurora.org> Add bindings doc for Qcom's smmu-v2 implementation. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Robin Murphy <robin.murphy@arm.com> --- .../devicetree/bindings/iommu/arm,smmu.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 8a6ffce12af5..a6504b37cc21 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -17,10 +17,16 @@ conditions. "arm,mmu-401" "arm,mmu-500" "cavium,smmu-v2" + "qcom,smmu-v2" depending on the particular implementation and/or the version of the architecture implemented. + Qcom SoCs must contain, as below, SoC-specific compatibles + along with "qcom,smmu-v2": + "qcom,msm8996-smmu-v2", "qcom,smmu-v2", + "qcom,sdm845-smmu-v2", "qcom,smmu-v2". + - reg : Base address and size of the SMMU. - #global-interrupts : The number of global interrupts exposed by the @@ -71,6 +77,22 @@ conditions. or using stream matching with #iommu-cells = <2>, and may be ignored if present in such cases. +- clock-names: List of the names of clocks input to the device. The + required list depends on particular implementation and + is as follows: + - for "qcom,smmu-v2": + - "bus": clock required for downstream bus access and + for the smmu ptw, + - "iface": clock required to access smmu's registers + through the TCU's programming interface. + - unspecified for other implementations. + +- clocks: Specifiers for all clocks listed in the clock-names property, + as per generic clock bindings. + +- power-domains: Specifiers for power domains required to be powered on for + the SMMU to operate, as per generic power domain bindings. + ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : @@ -137,3 +159,20 @@ conditions. iommu-map = <0 &smmu3 0 0x400>; ... }; + + /* Qcom's arm,smmu-v2 implementation */ + smmu4: iommu@d00000 { + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + reg = <0xd00000 0x10000>; + + #global-interrupts = <1>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc SMMU_MDP_AXI_CLK>, + <&mmcc SMMU_MDP_AHB_CLK>; + clock-names = "bus", "iface"; + }; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2018-11-16 11:24 UTC|newest] Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-11-16 11:24 [RESEND PATCH v17 0/5] iommu/arm-smmu: Add runtime pm/sleep support Vivek Gautam 2018-11-16 11:24 ` [RESEND PATCH v17 1/5] iommu/arm-smmu: Add pm_runtime/sleep ops Vivek Gautam 2018-11-16 11:24 ` [RESEND PATCH v17 2/5] iommu/arm-smmu: Invoke pm_runtime during probe, add/remove device Vivek Gautam [not found] ` <20181116112430.31248-3-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2018-11-21 17:37 ` Will Deacon 2018-11-21 17:37 ` Will Deacon [not found] ` <20181121173757.GA9801-5wv7dgnIgG8@public.gmane.org> 2018-11-22 12:02 ` Vivek Gautam 2018-11-22 12:02 ` Vivek Gautam [not found] ` <CAFp+6iEH7_XEcZNsbZfn6iBF5_o-ZKBj=DpturH7N85LU289qg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2018-11-23 18:36 ` Will Deacon 2018-11-23 18:36 ` Will Deacon [not found] ` <20181123183555.GE21183-5wv7dgnIgG8@public.gmane.org> 2018-11-26 6:03 ` Vivek Gautam 2018-11-26 6:03 ` Vivek Gautam [not found] ` <9064c01e-cef0-9306-078a-8d303cd6614b-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2018-11-26 11:26 ` Vivek Gautam 2018-11-26 11:26 ` Vivek Gautam [not found] ` <d66c5dbf-2e44-a915-14a0-1968c8ede832-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2018-11-26 19:31 ` Will Deacon 2018-11-26 19:31 ` Will Deacon [not found] ` <20181116112430.31248-1-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2018-11-16 11:24 ` [RESEND PATCH v17 3/5] iommu/arm-smmu: Add the device_link between masters and smmu Vivek Gautam 2018-11-16 11:24 ` Vivek Gautam 2018-11-16 11:24 ` Vivek Gautam [this message] 2018-11-16 11:24 ` [RESEND PATCH v17 4/5] dt-bindings: arm-smmu: Add bindings for qcom,smmu-v2 Vivek Gautam 2018-11-16 11:24 ` [RESEND PATCH v17 5/5] iommu/arm-smmu: Add support for qcom, smmu-v2 variant Vivek Gautam 2018-11-16 11:24 ` [RESEND PATCH v17 5/5] iommu/arm-smmu: Add support for qcom,smmu-v2 variant Vivek Gautam [not found] ` <20181116112430.31248-6-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2018-11-21 17:38 ` [RESEND PATCH v17 5/5] iommu/arm-smmu: Add support for qcom, smmu-v2 variant Will Deacon 2018-11-21 17:38 ` [RESEND PATCH v17 5/5] iommu/arm-smmu: Add support for qcom,smmu-v2 variant Will Deacon [not found] ` <20181121173803.GB9801-5wv7dgnIgG8@public.gmane.org> 2018-11-23 9:13 ` [RESEND PATCH v17 5/5] iommu/arm-smmu: Add support for qcom, smmu-v2 variant Vivek Gautam 2018-11-23 9:13 ` [RESEND PATCH v17 5/5] iommu/arm-smmu: Add support for qcom,smmu-v2 variant Vivek Gautam [not found] ` <CAFp+6iELH7Mw3Ue2ksEyV+Ac8hG8--Ki69xrPCA4F-AcireRow-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2018-11-23 9:22 ` Tomasz Figa 2018-11-23 9:22 ` Tomasz Figa [not found] ` <CAAFQd5B-bZR8dmjARb8L4oqgET2YAjXhexAO0GKAvU4JoVU=7g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2018-11-23 9:36 ` [RESEND PATCH v17 5/5] iommu/arm-smmu: Add support for qcom, smmu-v2 variant Vivek Gautam 2018-11-23 9:36 ` [RESEND PATCH v17 5/5] iommu/arm-smmu: Add support for qcom,smmu-v2 variant Vivek Gautam [not found] ` <CAFp+6iFhBRJWGY4Hj30tWedGpEUcnkBJrOvffmbpD2m9QMZB3A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2018-11-23 18:34 ` Will Deacon 2018-11-23 18:34 ` Will Deacon [not found] ` <20181123183428.GD21183-5wv7dgnIgG8@public.gmane.org> 2018-11-26 4:02 ` Tomasz Figa 2018-11-26 4:02 ` Tomasz Figa 2018-11-26 10:55 ` [RESEND PATCH v17 5/5] iommu/arm-smmu: Add support for qcom, smmu-v2 variant Vivek Gautam 2018-11-26 10:55 ` [RESEND PATCH v17 5/5] iommu/arm-smmu: Add support for qcom,smmu-v2 variant Vivek Gautam 2018-11-26 14:41 ` Thor Thayer 2018-11-26 14:41 ` Thor Thayer [not found] ` <ca287382-1d21-ad73-1648-00291a5da21b-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> 2018-11-26 17:55 ` [RESEND PATCH v17 5/5] iommu/arm-smmu: Add support for qcom, smmu-v2 variant Vivek Gautam 2018-11-26 17:55 ` [RESEND PATCH v17 5/5] iommu/arm-smmu: Add support for qcom,smmu-v2 variant Vivek Gautam
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