All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	Leo Li <leoyang.li@nxp.com>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	"will.deacon@arm.com" <will.deacon@arm.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>,
	"M.h. Lian" <minghuan.lian@nxp.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>,
	"Z.q. Hou" <zhiqiang.hou@nxp.com>
Subject: [PATCHv2 19/25] PCI: mobiveil: disabled IB and OB windows set by bootloader
Date: Tue, 20 Nov 2018 09:27:33 +0000	[thread overview]
Message-ID: <20181120092615.11680-20-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com>

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Disabled all inbound and outbound windows before set up the windows
in kernel, in case transactions match the window set by bootloader.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - no change

 .../controller/mobiveil/pcie-mobiveil-host.c   |  7 +++++++
 .../pci/controller/mobiveil/pcie-mobiveil.c    | 18 ++++++++++++++++++
 .../pci/controller/mobiveil/pcie-mobiveil.h    |  2 ++
 3 files changed, 27 insertions(+)

diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
index d1765d572f44..d028cdf31d0e 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
@@ -221,6 +221,13 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 {
 	u32 value, pab_ctrl, type;
 	struct resource_entry *win;
+	int i;
+
+	/* Disable all inbound/outbound windows */
+	for (i = 0; i < pcie->apio_wins; i++)
+		mobiveil_pcie_disable_ob_win(pcie, i);
+	for (i = 0; i < pcie->ppio_wins; i++)
+		mobiveil_pcie_disable_ib_win(pcie, i);
 
 	/* setup bus numbers */
 	value = csr_readl(pcie, PCI_PRIMARY_BUS);
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
index 370658d6546d..49d471b75925 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
@@ -226,3 +226,21 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
 
 	return -ETIMEDOUT;
 }
+
+void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num)
+{
+	u32 val;
+
+	val = csr_readl(pci, PAB_PEX_AMAP_CTRL(win_num));
+	val &= ~(1 << AMAP_CTRL_EN_SHIFT);
+	csr_writel(pci, val, PAB_PEX_AMAP_CTRL(win_num));
+}
+
+void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num)
+{
+	u32 val;
+
+	val = csr_readl(pci, PAB_AXI_AMAP_CTRL(win_num));
+	val &= ~(1 << WIN_ENABLE_SHIFT);
+	csr_writel(pci, val, PAB_AXI_AMAP_CTRL(win_num));
+}
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index eb4cb61291a8..81685840b378 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
@@ -171,6 +171,8 @@ void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
 			u64 pci_addr, u32 type, u64 size);
 void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
 			u64 pci_addr, u32 type, u64 size);
+void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num);
+void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num);
 u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
 void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size);
 
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: zhiqiang.hou@nxp.com (Z.q. Hou)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv2 19/25] PCI: mobiveil: disabled IB and OB windows set by bootloader
Date: Tue, 20 Nov 2018 09:27:33 +0000	[thread overview]
Message-ID: <20181120092615.11680-20-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com>

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Disabled all inbound and outbound windows before set up the windows
in kernel, in case transactions match the window set by bootloader.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - no change

 .../controller/mobiveil/pcie-mobiveil-host.c   |  7 +++++++
 .../pci/controller/mobiveil/pcie-mobiveil.c    | 18 ++++++++++++++++++
 .../pci/controller/mobiveil/pcie-mobiveil.h    |  2 ++
 3 files changed, 27 insertions(+)

diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
index d1765d572f44..d028cdf31d0e 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
@@ -221,6 +221,13 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 {
 	u32 value, pab_ctrl, type;
 	struct resource_entry *win;
+	int i;
+
+	/* Disable all inbound/outbound windows */
+	for (i = 0; i < pcie->apio_wins; i++)
+		mobiveil_pcie_disable_ob_win(pcie, i);
+	for (i = 0; i < pcie->ppio_wins; i++)
+		mobiveil_pcie_disable_ib_win(pcie, i);
 
 	/* setup bus numbers */
 	value = csr_readl(pcie, PCI_PRIMARY_BUS);
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
index 370658d6546d..49d471b75925 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
@@ -226,3 +226,21 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
 
 	return -ETIMEDOUT;
 }
+
+void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num)
+{
+	u32 val;
+
+	val = csr_readl(pci, PAB_PEX_AMAP_CTRL(win_num));
+	val &= ~(1 << AMAP_CTRL_EN_SHIFT);
+	csr_writel(pci, val, PAB_PEX_AMAP_CTRL(win_num));
+}
+
+void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num)
+{
+	u32 val;
+
+	val = csr_readl(pci, PAB_AXI_AMAP_CTRL(win_num));
+	val &= ~(1 << WIN_ENABLE_SHIFT);
+	csr_writel(pci, val, PAB_AXI_AMAP_CTRL(win_num));
+}
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index eb4cb61291a8..81685840b378 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
@@ -171,6 +171,8 @@ void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
 			u64 pci_addr, u32 type, u64 size);
 void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
 			u64 pci_addr, u32 type, u64 size);
+void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num);
+void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num);
 u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
 void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size);
 
-- 
2.17.1

  parent reply	other threads:[~2018-11-20  9:27 UTC|newest]

Thread overview: 167+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-20  9:25 [PATCHv2 00/25] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou
2018-11-20  9:25 ` Z.q. Hou
2018-11-20  9:25 ` Z.q. Hou
2018-11-20  9:25 ` [PATCHv2 01/25] PCI: mobiveil: uniform the register accessors Z.q. Hou
2018-11-20  9:25   ` Z.q. Hou
2018-11-20  9:25   ` Z.q. Hou
2018-11-20 10:17   ` M.h. Lian
2018-11-20 10:17     ` M.h. Lian
2018-11-20 10:17     ` M.h. Lian
2018-11-20  9:25 ` [PATCHv2 02/25] PCI: mobiveil: format the code without function change Z.q. Hou
2018-11-20  9:25   ` Z.q. Hou
2018-11-20  9:25   ` Z.q. Hou
2018-11-20 10:17   ` M.h. Lian
2018-11-20 10:17     ` M.h. Lian
2018-11-20 10:17     ` M.h. Lian
2018-11-20  9:25 ` [PATCHv2 03/25] PCI: mobiveil: correct the returned error number Z.q. Hou
2018-11-20  9:25   ` Z.q. Hou
2018-11-20  9:25   ` Z.q. Hou
2018-11-20 10:31   ` M.h. Lian
2018-11-20 10:31     ` M.h. Lian
2018-11-20 10:31     ` M.h. Lian
2018-11-20  9:26 ` [PATCHv2 04/25] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20 10:33   ` M.h. Lian
2018-11-20 10:33     ` M.h. Lian
2018-11-20 10:33     ` M.h. Lian
2018-11-20  9:26 ` [PATCHv2 05/25] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20 10:34   ` M.h. Lian
2018-11-20 10:34     ` M.h. Lian
2018-11-20 10:34     ` M.h. Lian
2018-11-20  9:26 ` [PATCHv2 06/25] PCI: mobiveil: replace the resource list iteration function Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20 10:35   ` M.h. Lian
2018-11-20 10:35     ` M.h. Lian
2018-11-20 10:35     ` M.h. Lian
2018-11-20  9:26 ` [PATCHv2 07/25] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20 10:35   ` M.h. Lian
2018-11-20 10:35     ` M.h. Lian
2018-11-20 10:35     ` M.h. Lian
2018-11-20  9:26 ` [PATCHv2 08/25] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20 10:59   ` M.h. Lian
2018-11-20 10:59     ` M.h. Lian
2018-11-20 10:59     ` M.h. Lian
2018-11-20  9:26 ` [PATCHv2 09/25] PCI: mobiveil: correct inbound/outbound window setup routines Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20 11:00   ` M.h. Lian
2018-11-20 11:00     ` M.h. Lian
2018-11-20 11:00     ` M.h. Lian
2018-11-20 11:00   ` M.h. Lian
2018-11-20 11:00     ` M.h. Lian
2018-11-20 11:00     ` M.h. Lian
2018-11-20  9:26 ` [PATCHv2 10/25] PCI: mobiveil: fix the INTx process error Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20 11:00   ` M.h. Lian
2018-11-20 11:00     ` M.h. Lian
2018-11-20 11:00     ` M.h. Lian
2018-11-20  9:26 ` [PATCHv2 11/25] PCI: mobiveil: only fix up the Class Code field Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20 11:01   ` M.h. Lian
2018-11-20 11:01     ` M.h. Lian
2018-11-20 11:01     ` M.h. Lian
2018-11-20  9:26 ` [PATCHv2 12/25] PCI: mobiveil: move out the link up waiting from mobiveil_host_init Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20 11:01   ` M.h. Lian
2018-11-20 11:01     ` M.h. Lian
2018-11-20 11:01     ` M.h. Lian
2018-11-20  9:26 ` [PATCHv2 13/25] PCI: mobiveil: move irq chained handler setup out of DT parse Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20  9:26   ` Z.q. Hou
2018-11-20 11:12   ` M.h. Lian
2018-11-20 11:12     ` M.h. Lian
2018-11-20 11:12     ` M.h. Lian
2018-11-20  9:27 ` [PATCHv2 14/25] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20 11:13   ` M.h. Lian
2018-11-20 11:13     ` M.h. Lian
2018-11-20 11:13     ` M.h. Lian
2018-11-20 11:24   ` M.h. Lian
2018-11-20 11:24     ` M.h. Lian
2018-11-20 11:24     ` M.h. Lian
2018-11-20  9:27 ` [PATCHv2 15/25] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20 11:25   ` M.h. Lian
2018-11-20 11:25     ` M.h. Lian
2018-11-20 11:25     ` M.h. Lian
2018-11-20  9:27 ` [PATCHv2 16/25] PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20 11:25   ` M.h. Lian
2018-11-20 11:25     ` M.h. Lian
2018-11-20 11:25     ` M.h. Lian
2018-11-20  9:27 ` [PATCHv2 17/25] PCI: mobiveil: fix the checking of valid device Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20 11:26   ` M.h. Lian
2018-11-20 11:26     ` M.h. Lian
2018-11-20 11:26     ` M.h. Lian
2018-11-20  9:27 ` [PATCHv2 18/25] PCI: mobiveil: continue to initialize the host upon no PCIe link Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20 11:26   ` M.h. Lian
2018-11-20 11:26     ` M.h. Lian
2018-11-20 11:26     ` M.h. Lian
2018-11-20  9:27 ` Z.q. Hou [this message]
2018-11-20  9:27   ` [PATCHv2 19/25] PCI: mobiveil: disabled IB and OB windows set by bootloader Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20 11:26   ` M.h. Lian
2018-11-20 11:26     ` M.h. Lian
2018-11-20 11:26     ` M.h. Lian
2018-11-20  9:27 ` [PATCHv2 20/25] PCI: mobiveil: add Byte and Half-Word width register accessors Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20 11:27   ` M.h. Lian
2018-11-20 11:27     ` M.h. Lian
2018-11-20 11:27     ` M.h. Lian
2018-11-20  9:27 ` [PATCHv2 21/25] PCI: mobiveil: make mobiveil_host_init can be used to re-init host Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20 11:30   ` M.h. Lian
2018-11-20 11:30     ` M.h. Lian
2018-11-20 11:30     ` M.h. Lian
2018-11-20  9:27 ` [PATCHv2 22/25] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20 11:31   ` M.h. Lian
2018-11-20 11:31     ` M.h. Lian
2018-11-20 11:31     ` M.h. Lian
2018-12-05 22:38   ` Rob Herring
2018-12-05 22:38     ` Rob Herring
2018-12-05 22:38     ` Rob Herring
2018-12-05 22:40     ` Rob Herring
2018-12-05 22:40       ` Rob Herring
2018-12-05 22:40       ` Rob Herring
2018-12-11  9:50     ` Z.q. Hou
2018-12-11  9:50       ` Z.q. Hou
2018-11-20  9:27 ` [PATCHv2 23/25] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20  9:27   ` Z.q. Hou
2018-11-20 11:32   ` M.h. Lian
2018-11-20 11:32     ` M.h. Lian
2018-11-20 11:32     ` M.h. Lian
2018-11-20  9:28 ` [PATCHv2 24/25] arm64: dts: freescale: lx2160a: add pcie DT nodes Z.q. Hou
2018-11-20  9:28   ` Z.q. Hou
2018-11-20  9:28   ` Z.q. Hou
2018-11-20 11:32   ` M.h. Lian
2018-11-20 11:32     ` M.h. Lian
2018-11-20 11:32     ` M.h. Lian
2018-11-20  9:28 ` [PATCHv2 25/25] arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 Z.q. Hou
2018-11-20  9:28   ` Z.q. Hou
2018-11-20  9:28   ` Z.q. Hou
2018-11-20 11:33   ` M.h. Lian
2018-11-20 11:33     ` M.h. Lian
2018-11-20 11:33     ` M.h. Lian

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181120092615.11680-20-Zhiqiang.Hou@nxp.com \
    --to=zhiqiang.hou@nxp.com \
    --cc=bhelgaas@google.com \
    --cc=catalin.marinas@arm.com \
    --cc=devicetree@vger.kernel.org \
    --cc=l.subrahmanya@mobiveil.co.in \
    --cc=leoyang.li@nxp.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=mark.rutland@arm.com \
    --cc=minghuan.lian@nxp.com \
    --cc=mingkai.hu@nxp.com \
    --cc=robh+dt@kernel.org \
    --cc=shawnguo@kernel.org \
    --cc=will.deacon@arm.com \
    --cc=xiaowei.bao@nxp.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.