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From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Manasi Navare <manasi.d.navare@intel.com>
Subject: [PATCH v10 01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
Date: Tue, 20 Nov 2018 10:37:14 -0800	[thread overview]
Message-ID: <20181120183736.28054-2-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20181120183736.28054-1-manasi.d.navare@intel.com>

DSC DPCD color depth register advertises its color depth capabilities
by setting each of the bits that corresponding to a specific color
depth. This patch defines those specific color depths and adds
a helper to return an array of color depth capabilities.

v2:
* Simplify the logic (Ville)

Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 14 ++++++++------
 include/drm/drm_dp_helper.h     |  3 ++-
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 6d483487f2b4..2d6c491a0542 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1428,17 +1428,19 @@ u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
 }
 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
 
-u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+					 u8 dsc_bpc[3])
 {
+	int num_bpc = 0;
 	u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
 
 	if (color_depth & DP_DSC_12_BPC)
-		return 12;
+		dsc_bpc[num_bpc++] = 12;
 	if (color_depth & DP_DSC_10_BPC)
-		return 10;
+		dsc_bpc[num_bpc++] = 10;
 	if (color_depth & DP_DSC_8_BPC)
-		return 8;
+		dsc_bpc[num_bpc++] = 8;
 
-	return 0;
+	return num_bpc;
 }
-EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
+EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 3314e91f6eb3..5736c942c85b 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1123,7 +1123,8 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
 				   bool is_edp);
 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
-u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE]);
+int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
+					 u8 dsc_bpc[3]);
 
 static inline bool
 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
-- 
2.19.1

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  reply	other threads:[~2018-11-20 18:37 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-20 18:37 [PATCH v10 00/23] Respin of remaining DSC + FEC patches Manasi Navare
2018-11-20 18:37 ` Manasi Navare [this message]
2018-11-27 13:47   ` [PATCH v10 01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Ville Syrjälä
2018-11-27 17:44   ` Srivatsa, Anusha
2018-11-20 18:37 ` [PATCH v10 02/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-20 18:37 ` [PATCH v10 03/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-11-20 18:37 ` [PATCH v10 04/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-11-20 18:37 ` [PATCH v10 05/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-20 18:37 ` [PATCH v10 06/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-11-20 18:37 ` [PATCH v10 07/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-20 18:37 ` [PATCH v10 08/23] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-27 13:57   ` Ville Syrjälä
2018-11-27 17:29     ` Manasi Navare
2018-11-20 18:37 ` [PATCH v10 09/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-20 18:37 ` [PATCH v10 10/23] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-20 18:37 ` [PATCH v10 11/23] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-20 18:37 ` [PATCH v10 12/23] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-20 18:37 ` [PATCH v10 13/23] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-20 18:37 ` [PATCH v10 14/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-20 18:37 ` [PATCH v10 15/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-20 18:37 ` [PATCH v10 16/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-20 18:37 ` [PATCH v10 17/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-20 18:37 ` [PATCH v10 18/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-20 18:37 ` [PATCH v10 19/23] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-20 18:37 ` [PATCH v10 20/23] i915/dp/fec: Add fec_enable to the crtc state Manasi Navare
2018-11-27 17:46   ` Manasi Navare
2018-11-20 18:37 ` [PATCH v10 21/23] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Manasi Navare
2018-11-20 18:37 ` [PATCH v10 22/23] i915/dp/fec: Configure the Forward Error Correction bits Manasi Navare
2018-11-27 17:47   ` Manasi Navare
2018-11-20 18:37 ` [PATCH v10 23/23] drm/i915/fec: Disable FEC state Manasi Navare
2018-11-20 18:58 ` ✗ Fi.CI.CHECKPATCH: warning for Respin of remaining DSC + FEC patches Patchwork
2018-11-20 19:06 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-20 19:29 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-21  6:54 ` ✓ Fi.CI.IGT: " Patchwork
2018-11-29 20:57 ` [PATCH v10 00/23] " Manasi Navare

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