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From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: [CI v11 16/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
Date: Tue, 27 Nov 2018 10:00:36 -0800	[thread overview]
Message-ID: <20181127180043.21459-16-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20181127180043.21459-1-manasi.d.navare@intel.com>

DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.

v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond drm-tip

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_vdsc.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index 0e72520abdfc..2cc933b57d94 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -976,6 +976,25 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
 	}
 }
 
+static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
+				       const struct intel_crtc_state *crtc_state)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
+	struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
+
+	/* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
+	drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp);
+
+	/* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
+	drm_dsc_pps_infoframe_pack(&dp_dsc_pps_sdp, vdsc_cfg);
+
+	intel_dig_port->write_infoframe(encoder, crtc_state,
+					DP_SDP_PPS, &dp_dsc_pps_sdp,
+					sizeof(dp_dsc_pps_sdp));
+}
+
 void intel_dsc_enable(struct intel_encoder *encoder,
 		      const struct intel_crtc_state *crtc_state)
 {
@@ -985,5 +1004,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
 
 	intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
 
+	intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+
 	return;
 }
-- 
2.19.1

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  parent reply	other threads:[~2018-11-27 18:00 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-27 18:00 [CI v11 01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Manasi Navare
2018-11-27 18:00 ` [CI v11 02/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-27 18:00 ` [CI v11 03/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-11-27 18:00 ` [CI v11 04/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-11-27 18:00 ` [CI v11 05/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-27 18:00 ` [CI v11 06/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-11-27 18:00 ` [CI v11 07/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-27 18:00 ` [CI v11 08/23] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-27 18:00 ` [CI v11 09/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-27 18:00 ` [CI v11 10/23] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-27 18:00 ` [CI v11 11/23] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-27 18:00 ` [CI v11 12/23] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-27 18:00 ` [CI v11 13/23] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-27 18:00 ` [CI v11 14/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-27 18:00 ` [CI v11 15/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-27 18:00 ` Manasi Navare [this message]
2018-11-27 18:00 ` [CI v11 17/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-27 18:00 ` [CI v11 18/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-27 18:00 ` [CI v11 19/23] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-27 18:00 ` [CI v11 20/23] i915/dp/fec: Add fec_enable to the crtc state Manasi Navare
2018-11-27 18:00 ` [CI v11 21/23] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Manasi Navare
2018-11-27 18:00 ` [CI v11 22/23] i915/dp/fec: Configure the Forward Error Correction bits Manasi Navare
2018-11-27 18:00 ` [CI v11 23/23] drm/i915/fec: Disable FEC state Manasi Navare
2018-11-27 18:47 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v11,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Patchwork
2018-11-27 18:55 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-27 19:12 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-28  2:20 ` ✗ Fi.CI.IGT: failure " Patchwork

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