From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 3/5] drm/i915/selftests: Terminate hangcheck sanitycheck forcibly
Date: Wed, 28 Nov 2018 20:34:33 +0000 [thread overview]
Message-ID: <20181128203435.22907-3-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20181128203435.22907-1-chris@chris-wilson.co.uk>
If all else fails and we are stuck eternally waiting for the undying
request, abandon all hope.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index defe671130ab..a48fbe2557ea 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -308,6 +308,7 @@ static int igt_hang_sanitycheck(void *arg)
goto unlock;
for_each_engine(engine, i915, id) {
+ struct igt_wedge_me w;
long timeout;
if (!intel_engine_can_store_dword(engine))
@@ -328,9 +329,14 @@ static int igt_hang_sanitycheck(void *arg)
i915_request_add(rq);
- timeout = i915_request_wait(rq,
- I915_WAIT_LOCKED,
- MAX_SCHEDULE_TIMEOUT);
+ timeout = 0;
+ igt_wedge_on_timeout(&w, i915, HZ / 10 /* 100ms timeout*/)
+ timeout = i915_request_wait(rq,
+ I915_WAIT_LOCKED,
+ MAX_SCHEDULE_TIMEOUT);
+ if (i915_terminally_wedged(&i915->gpu_error))
+ timeout = -EIO;
+
i915_request_put(rq);
if (timeout < 0) {
--
2.20.0.rc1
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next prev parent reply other threads:[~2018-11-28 20:34 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-28 20:34 [PATCH 1/5] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Chris Wilson
2018-11-28 20:34 ` [PATCH 2/5] drm/i915: Allocate a common scratch page Chris Wilson
2018-11-28 20:34 ` Chris Wilson [this message]
2018-11-28 20:34 ` [PATCH 4/5] drm/i915/selftests: Reorder request allocation vs vma pinning Chris Wilson
2018-11-28 20:34 ` [PATCH 5/5] drm/i915: Pipeline PDP updates for Braswell Chris Wilson
2018-11-28 21:08 ` ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Patchwork
2018-11-28 21:27 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-29 7:53 ` ✓ Fi.CI.IGT: " Patchwork
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