From: Anup Patel <anup@brainfault.org> To: Palmer Dabbelt <palmer@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <marc.zyngier@arm.com> Cc: Atish Patra <atish.patra@wdc.com>, Christoph Hellwig <hch@infradead.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel <anup@brainfault.org> Subject: [PATCH v3 3/6] irqchip: sifive-plic: More flexible plic_irq_toggle() Date: Fri, 30 Nov 2018 13:32:04 +0530 [thread overview] Message-ID: <20181130080207.20505-4-anup@brainfault.org> (raw) In-Reply-To: <20181130080207.20505-1-anup@brainfault.org> We make plic_irq_toggle() more generic so that we can enable/disable hwirq for given cpumask. This generic plic_irq_toggle() will be eventually used to implement set_affinity for PLIC driver. Signed-off-by: Anup Patel <anup@brainfault.org> --- drivers/irqchip/irq-sifive-plic.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 48bee877e0f1..d4433399eb89 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -78,8 +78,7 @@ struct plic_hw { static struct plic_hw plic; -static inline void plic_toggle(struct plic_handler *handler, - int hwirq, int enable) +static void plic_toggle(struct plic_handler *handler, int hwirq, int enable) { u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32); u32 hwirq_mask = 1 << (hwirq % 32); @@ -92,27 +91,27 @@ static inline void plic_toggle(struct plic_handler *handler, raw_spin_unlock(&handler->enable_lock); } -static inline void plic_irq_toggle(struct irq_data *d, int enable) +static void plic_irq_toggle(const struct cpumask *mask, int hwirq, int enable) { int cpu; - writel(enable, plic.regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); - for_each_cpu(cpu, irq_data_get_affinity_mask(d)) { + writel(enable, plic.regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID); + for_each_cpu(cpu, mask) { struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); if (handler->present) - plic_toggle(handler, d->hwirq, enable); + plic_toggle(handler, hwirq, enable); } } static void plic_irq_enable(struct irq_data *d) { - plic_irq_toggle(d, 1); + plic_irq_toggle(irq_data_get_affinity_mask(d), d->hwirq, 1); } static void plic_irq_disable(struct irq_data *d) { - plic_irq_toggle(d, 0); + plic_irq_toggle(irq_data_get_affinity_mask(d), d->hwirq, 0); } static struct irq_chip plic_chip = { -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org> To: Palmer Dabbelt <palmer@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <marc.zyngier@arm.com> Cc: Christoph Hellwig <hch@infradead.org>, Atish Patra <atish.patra@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel <anup@brainfault.org> Subject: [PATCH v3 3/6] irqchip: sifive-plic: More flexible plic_irq_toggle() Date: Fri, 30 Nov 2018 13:32:04 +0530 [thread overview] Message-ID: <20181130080207.20505-4-anup@brainfault.org> (raw) In-Reply-To: <20181130080207.20505-1-anup@brainfault.org> We make plic_irq_toggle() more generic so that we can enable/disable hwirq for given cpumask. This generic plic_irq_toggle() will be eventually used to implement set_affinity for PLIC driver. Signed-off-by: Anup Patel <anup@brainfault.org> --- drivers/irqchip/irq-sifive-plic.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 48bee877e0f1..d4433399eb89 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -78,8 +78,7 @@ struct plic_hw { static struct plic_hw plic; -static inline void plic_toggle(struct plic_handler *handler, - int hwirq, int enable) +static void plic_toggle(struct plic_handler *handler, int hwirq, int enable) { u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32); u32 hwirq_mask = 1 << (hwirq % 32); @@ -92,27 +91,27 @@ static inline void plic_toggle(struct plic_handler *handler, raw_spin_unlock(&handler->enable_lock); } -static inline void plic_irq_toggle(struct irq_data *d, int enable) +static void plic_irq_toggle(const struct cpumask *mask, int hwirq, int enable) { int cpu; - writel(enable, plic.regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); - for_each_cpu(cpu, irq_data_get_affinity_mask(d)) { + writel(enable, plic.regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID); + for_each_cpu(cpu, mask) { struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); if (handler->present) - plic_toggle(handler, d->hwirq, enable); + plic_toggle(handler, hwirq, enable); } } static void plic_irq_enable(struct irq_data *d) { - plic_irq_toggle(d, 1); + plic_irq_toggle(irq_data_get_affinity_mask(d), d->hwirq, 1); } static void plic_irq_disable(struct irq_data *d) { - plic_irq_toggle(d, 0); + plic_irq_toggle(irq_data_get_affinity_mask(d), d->hwirq, 0); } static struct irq_chip plic_chip = { -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2018-11-30 8:02 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-11-30 8:02 [PATCH v3 0/6] IRQ affinity support in PLIC driver Anup Patel 2018-11-30 8:02 ` Anup Patel 2018-11-30 8:02 ` [PATCH v3 1/6] irqchip: sifive-plic: Pre-compute context hart base and enable base Anup Patel 2018-11-30 8:02 ` Anup Patel 2018-12-17 18:25 ` Christoph Hellwig 2018-12-17 18:25 ` Christoph Hellwig 2018-12-18 8:30 ` Anup Patel 2018-12-18 8:30 ` Anup Patel 2018-11-30 8:02 ` [PATCH v3 2/6] irqchip: sifive-plic: Add struct plic_hw for global PLIC HW details Anup Patel 2018-11-30 8:02 ` Anup Patel 2018-12-17 18:24 ` Christoph Hellwig 2018-12-17 18:24 ` Christoph Hellwig 2018-12-18 8:25 ` Anup Patel 2018-12-18 8:25 ` Anup Patel 2018-11-30 8:02 ` Anup Patel [this message] 2018-11-30 8:02 ` [PATCH v3 3/6] irqchip: sifive-plic: More flexible plic_irq_toggle() Anup Patel 2018-12-17 18:27 ` Christoph Hellwig 2018-12-17 18:27 ` Christoph Hellwig 2018-12-18 8:50 ` Anup Patel 2018-12-18 8:50 ` Anup Patel 2018-12-19 16:28 ` Christoph Hellwig 2018-12-19 16:28 ` Christoph Hellwig 2018-12-27 5:27 ` Anup Patel 2018-12-27 5:27 ` Anup Patel 2018-11-30 8:02 ` [PATCH v3 4/6] irqchip: sifive-plic: Add warning in plic_init() if handler already present Anup Patel 2018-11-30 8:02 ` Anup Patel 2018-12-17 18:28 ` Christoph Hellwig 2018-12-17 18:28 ` Christoph Hellwig 2018-12-18 8:36 ` Anup Patel 2018-12-18 8:36 ` Anup Patel 2018-11-30 8:02 ` [PATCH v3 5/6] irqchip: sifive-plic: Differentiate between PLIC handler and context Anup Patel 2018-11-30 8:02 ` Anup Patel 2018-11-30 8:02 ` [PATCH v3 6/6] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host Anup Patel 2018-11-30 8:02 ` Anup Patel 2018-12-17 18:32 ` Christoph Hellwig 2018-12-17 18:32 ` Christoph Hellwig 2018-12-18 10:32 ` Anup Patel 2018-12-18 10:32 ` Anup Patel 2018-12-17 9:37 ` [PATCH v3 0/6] IRQ affinity support in PLIC driver Anup Patel 2018-12-17 9:37 ` Anup Patel 2018-12-20 20:40 ` Palmer Dabbelt 2018-12-20 20:40 ` Palmer Dabbelt
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